How do I write to file? Testbench basics for beginners in Verilog!

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  • Опубликовано: 11 дек 2024

Комментарии • 13

  • @FPGAsforBeginners
    @FPGAsforBeginners  3 года назад +3

    Hi All! I'll be doing a file-reading video - that's going to be its own thing. It'll be part of the DSP example series that's coming up.
    And here's the subreddit link if you're interested: www.reddit.com/r/hdlforbeginners

  • @joerit633
    @joerit633 2 года назад

    Very helpful!! Thank you Stacey!!

  • @varunsharma3860
    @varunsharma3860 3 года назад +3

    Hi Stacey,
    Thanks for showing how to dump data to a file in a testbench 👍
    Can you also show how to inject stimulus to the DUT by reading through a file?
    Thanks

    • @FPGAsforBeginners
      @FPGAsforBeginners  3 года назад +1

      Hi! Yes I will. That's going to be it's own video.

  • @mateuszlesko5301
    @mateuszlesko5301 2 года назад

    Amazingly helpful channel, keep going !

  • @enriqeat
    @enriqeat Год назад

    Does forcing clocks and inputs in the behavioral simulation of vivado works the same as writing a testbench and the running the simulation?

  • @deathmaster4035
    @deathmaster4035 2 года назад

    EDIT: THANKS A LOT. :)
    Hi. I am trying to write a testbench for a file. I am so confused here. Are write_to_file and write_to_file_i (@4:17) two separate modules or are they the same module which you explained?
    Also, do I need to create a text file separately first or is that going to be created during the simulation?
    EDIT: Also, where are you supposed to call the write_to_file module? Inside the test bench? Or inside our top module?
    EDIT: One more question, If we are supposed to create a text file ourselves? Where do we put the file? A vivado project has multiple folders.
    EDIT: I figured out everything.
    EDIT: One last question: How to run the simulation for a specified duration of time?

  • @cccmmm1234
    @cccmmm1234 Год назад

    Hi Stacey
    Do you run your test bench in Vivado or something else?

  • @tomo4294
    @tomo4294 2 года назад

    Was wondering whether something like this has happened to you.
    I encountered an issue trying to read a .txt file from a test bench in vivado simulation. There was a file descriptor error, which was only solved by giving the absolute path of the file. What would be the way around this? Thanks

    • @FPGAsforBeginners
      @FPGAsforBeginners  2 года назад

      This can be an issue if the simulator working directory is different from the project working directory. So sometimes the relative path is difficult to determine, which is why using the absolute path fixed the problem.

    • @tomo4294
      @tomo4294 2 года назад

      ​@@FPGAsforBeginners Thank you