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FPGAs for Beginners
Южно-Африканская Республика
Добавлен 6 июл 2021
Hi! I'm Stacey and I've been a RTL Design Engineer for 12 years! Here I post videos discussing how beginners can improve their FPGA skills!
AXI-Stream Arbiter example
Hi, I'm Stacey, and in this video I go over my AXI-Stream Arbiter example
Collaboration: ruclips.net/video/78tkdc6Lq_8/видео.html
Toolbox: github.com/HDLForBeginners/Toolbox/tree/main
Ethernet video: ruclips.net/video/zTsHbEIOM2A/видео.html
UART video: ruclips.net/video/hVMeU2ThgNw/видео.html
AXI Stream video: ruclips.net/video/GyYmSZZor1s/видео.html
Generate statement video: ruclips.net/video/3tUp621Lf7o/видео.html
FPGA essentials (sync/async logic): ruclips.net/video/9umFgzntXTw/видео.html
0:00 Intro
2:38 Arbiter introduction
5:48 Arbiter top-level
21:33 Outro
Buy me a coffee to support my channel: www.buymeacoffee.com/FPGAsforbeginners
Collaboration: ruclips.net/video/78tkdc6Lq_8/видео.html
Toolbox: github.com/HDLForBeginners/Toolbox/tree/main
Ethernet video: ruclips.net/video/zTsHbEIOM2A/видео.html
UART video: ruclips.net/video/hVMeU2ThgNw/видео.html
AXI Stream video: ruclips.net/video/GyYmSZZor1s/видео.html
Generate statement video: ruclips.net/video/3tUp621Lf7o/видео.html
FPGA essentials (sync/async logic): ruclips.net/video/9umFgzntXTw/видео.html
0:00 Intro
2:38 Arbiter introduction
5:48 Arbiter top-level
21:33 Outro
Buy me a coffee to support my channel: www.buymeacoffee.com/FPGAsforbeginners
Просмотров: 1 362
Видео
Collaboration with Robert Feranec and new open source SystemVerilog toolbox
Просмотров 2,1 тыс.Месяц назад
Hi, I'm Stacey, and in this video I talk about my collaboration with Robert Feranec and new open source SystemVerilog toolbox Collaboration: ruclips.net/video/78tkdc6Lq_8/видео.html Toolbox: github.com/HDLForBeginners/Toolbox/tree/main Ethernet video: ruclips.net/video/zTsHbEIOM2A/видео.html UART video: ruclips.net/video/hVMeU2ThgNw/видео.html Buy me a coffee to support my channel: www.buymeaco...
The Critical FPGA Basics: Always blocks, Inferred latches, and why the FPGA needs a clock, anyway?!
Просмотров 3,4 тыс.Месяц назад
Hi, I'm Stacey, and in this video I talk about everything from asynchronous logic, why the FPGA even needs a clock, and inferred latches! 0:00 Intro 0:38 Always blocks 8:27: Why the FPGA needs a clock, and static timing analysis 13:00 Registers and their function 16:00 Synchronus and Asynchronus logic 18:40 Asynchronus loopback paths and inferred latches 23:50 Avoiding inferred latches 27:05 Su...
5000 Subscribers! Answering your frequently-asked questions!
Просмотров 2 тыс.10 месяцев назад
Hi, I'm Stacey, and in this video I answer some of your questions! Online language learning: hdlbits.01xz.net/wiki/Main_Page chipdev.io/ edaplayground.com/ www.makerchip.com/ Risc-V courses: www.edx.org/learn/computer-science/the-linux-foundation-introduction-to-risc-v www.edx.org/learn/design/the-linux-foundation-building-a-risc-v-cpu-core www.edx.org/learn/computer-programming/the-linux-found...
Free FPGA training and resources!
Просмотров 5 тыс.11 месяцев назад
Hi, I'm Stacey, and in this video I share some free webinar series! Links: bltinc.com/homepage/xilinx-training/blt-webinar-series/ www.doulos.com/webinars/ www.intel.com/content/www/us/en/developer/learn/webinars.html Buy me a coffee to support my channel: www.buymeacoffee.com/fpgasforbeginners
Zynq Part 3: Combining my own HDL with the Vivado block diagram!
Просмотров 8 тыс.Год назад
Hi, I'm Stacey, and in this video I show how I add my own logic beside the block diagram in Vivado. Github Code: github.com/HDLForBeginners/Examples/tree/main/ZynqSeries Buy me a coffee to support my channel: www.buymeacoffee.com/fpgasforbeginners
ILA in a Zynq: View signals in hardware!
Просмотров 6 тыс.Год назад
Hi, I'm Stacey, and in this video I show you how to add an ILA in a zynq! (Also works for other Vivado-based Xilinx devices! Buy me a coffee to support my channel: www.buymeacoffee.com/fpgasforbeginners
Zynq Part 2: Zynq Vitis Example with PL Fabric GPIO and BRAM
Просмотров 14 тыс.Год назад
Hi, I'm Stacey, and in this video I go over part 2 in my zynq series, using Vitis! Part 1: ruclips.net/video/UZ3FnZNlcWk/видео.html Github Code: github.com/HDLForBeginners/Examples/tree/main/ZynqSeries Buy me a coffee to support my channel: www.buymeacoffee.com/fpgasforbeginners
Zynq Part 1: Vivado block diagram (no Verilog/VHDL necessary!)
Просмотров 23 тыс.Год назад
Hi, I'm Stacey, and in this video I show the vivado side of a basic Zynq project with no VHDL/Verilog required. Not Sponsored, I just use this software a lot! Download vivado here: www.xilinx.com/support/download.html Buy me a coffee to support my channel: www.buymeacoffee.com/fpgasforbeginners
Is chatGPT going to take my job? How well can chatGPT write Verilog?
Просмотров 2,6 тыс.Год назад
Music and Editing by @CapoXProductions Buy me a coffee to support my channel: www.buymeacoffee.com/fpgasforbeginners
AXI Part 3: AXI-Lite testbench (briefly)
Просмотров 2,2 тыс.Год назад
Hi, I'm Stacey, and in this video I go over the axi tb briefly First 2 parts: ruclips.net/video/p5RIVEuxUds/видео.html ruclips.net/video/y0z5Cg4gp6k/видео.html Github Code: github.com/HDLForBeginners/Examples/blob/main/axi_lite/ Buy me a coffee to support my channel: www.buymeacoffee.com/fpgasforbeginners
AXI Introduction Part 2: AXI-Lite state machine example explained!
Просмотров 4,9 тыс.Год назад
AXI Introduction Part 2: AXI-Lite state machine example explained!
AXI Introduction Part 1: How AXI works and AXI-Lite transaction example
Просмотров 17 тыс.Год назад
AXI Introduction Part 1: How AXI works and AXI-Lite transaction example
Reading from and writing to file: My PDM testbench from start to finish.
Просмотров 2,3 тыс.Год назад
Reading from and writing to file: My PDM testbench from start to finish.
When and how to use the Multiplier IP core
Просмотров 4,2 тыс.2 года назад
When and how to use the Multiplier IP core
FPGA Audio to my PC over Ethernet! PDM Microphone and CIC filter explained!
Просмотров 8 тыс.2 года назад
FPGA Audio to my PC over Ethernet! PDM Microphone and CIC filter explained!
Handling Ethernet FIFO overflows in SystemVerilog! How to keep packets intact above line rate!
Просмотров 8 тыс.2 года назад
Handling Ethernet FIFO overflows in SystemVerilog! How to keep packets intact above line rate!
Receiving packets over Ethernet using Python
Просмотров 6 тыс.2 года назад
Receiving packets over Ethernet using Python
How to use the clocking wizard IP: creating a 50Mhz clock from 100Mhz
Просмотров 7 тыс.2 года назад
How to use the clocking wizard IP: creating a 50Mhz clock from 100Mhz
A quick and easy Ethernet Frame state machine, explained from start to finish!
Просмотров 11 тыс.2 года назад
A quick and easy Ethernet Frame state machine, explained from start to finish!
My Linux + Vivado development environment!
Просмотров 3,8 тыс.2 года назад
My Linux Vivado development environment!
Flashing a LED with Vivado and a Nexys A7 FPGA board: Step by step walkthrough!
Просмотров 7 тыс.2 года назад
Flashing a LED with Vivado and a Nexys A7 FPGA board: Step by step walkthrough!
Polynomial example part 2! Final window code with pipelining!
Просмотров 2,1 тыс.2 года назад
Polynomial example part 2! Final window code with pipelining!
Tips for working on a engineering design team as an intern or new graduate!
Просмотров 1,9 тыс.2 года назад
Tips for working on a engineering design team as an intern or new graduate!
Fixing failed timing, a practical example in verilog!
Просмотров 5 тыс.2 года назад
Fixing failed timing, a practical example in verilog!
FPGA unboxing and chat: Why I started this channel and future plans!
Просмотров 1,5 тыс.3 года назад
FPGA unboxing and chat: Why I started this channel and future plans!
Fixed point basics in Verilog for Beginners! Continuation of polynomial example.
Просмотров 7 тыс.3 года назад
Fixed point basics in Verilog for Beginners! Continuation of polynomial example.
Miller Kimberly Smith Kevin Rodriguez Richard
Hi, I’ve been following your videos, and they are really good. I wanted to ask for a favor, if you don’t mind. Could you please make another video on STA with a real-time example, such as a FIFO or some protocols? In that video, it would be great if you could explain how to solve timing issues like negative slack, setup, and hold time violations.
Could you please make a tutorial on how to re-upload a .mem file after making changes to it so that we don’t need to re-generate a bitstream? Many thanks!
Hello! Could you please help : can't find in new Vitis " Documentation link" (the one that is VSCode based) and peripheral examples(only can see Templates for projects)
afrikaans is my favorite accent
The block design or Altera's Platform Designer are very impressive tools to design. However, knowing that a microblaze/nios connects to an interrupt controller for example is what I still don't understand. Do you need to take a course/learn about computer architecture to understand all those blocks or do the vendors provide them. I feel like if you told me to design LED toggling, I wouldn't know which blocks to connect or how to connect them even though I know where to click on the software to access them. How would I go about that?
You should consider teaching as a job.
TOP
Thank you
Hi Stacy, I just discovered your channel. I was wondering if you have an example streaming UDP data to a remote host. I'm trying to receive the stream with a python socket, and account of dropped packets (where I'm using a Zynq to transfer the data). Thank you so much!
For XBram_WriteReg as well as for ReadReg, why you have used device_id instead of base_address, please answer as i am going crazy abt it
Is there a video showing how to use a pmod pin as an external clock? Sometimes I think I works for some pins and not for others and I dont completely understand why
THIS WAS ONE YEAR AGO ... WHAT ABOUT NOW ?
I should try again and see!
Thank you for useful video !! ^^
When you hit Run and Launch, where actually is the program running?
On the processor on my Zybo board!
Can you share basic videos of explaining the inter clock and intra clock issue
Finally, a tutoral on Xilinix SoC's that makes sense.
Don't know if it is easy to do but can you make videos with higher resolution? I mean it's a bit hard to read the code in 720p. Overall it's a nice lecture, good job!
I absolutely love how involved you are throughout. Amazing.
great
Nice video
Hands up everyone who has a favorite state machine! 👍
Interesting video, the idea of axi was alien to me until yesterday when I binged your videos. I understand it more and it makes a lot more sense for how more complex FPGA designs can exist. A question I do have though, when it comes to design architecture. If we look at your microphone to udp example. If you wanted to have a programmable gain or frequency response, or anything about the design to be programmable, how would you incorporate that? My thought would be you could use registers in a memory block to hold configuration data and through the axi stream set those registers over udp. Then your microphone or other elements can read those configuration registers. Is this how it would be done or am I completely off?
Really nice vid, was just struggling with this. Would be interested to learn about pipelining an axi stream without breaking the backpressure
That is essentially what the FIFO does. AXI is a very strict specification. You can't really modify it.
Another method is using skid buffers - essentially 1 deep FIFOs.
Exactly what I was going to say. Skid buffer.
Hi stacy, would you be inclined to do private lessons via zoom call?
Hi David, I'm not taking on any more clients at the moment, but will be making more videos in my spare time. You're welcome to suggest a video idea if there's anything specific you're interested in.
@@FPGAsforBeginners I struggle with vivado.. petalux.. the mpsoc platform has alluded me. I have a good grasp on fundamentals, system Verilog, verilog, hdl, that I can do fine, hard logic coding also isnt a struggle. Its Xilinx's software stack that's always humbling me. I find myself in Quartus alot, just to avoid feeling bloated and inefficient with vivado. Could you do a fresh onboarding video? perhaps targeting an mpsoc platform, perhaps a zcu102.. A hands on with Xilinx primitives would be cool, DSP preferably. Thanks for being awesome 💖
It's really helpful for beginner like me. Have you implement that neural network on fpga. Thanks
Thank you very much for your materials! ❤
*Summary* * *(**0:00**)* *Purpose:* The video explains an AXI-Stream Arbiter example designed to debug data streams. It combines multiple AXI-Stream inputs and outputs them to a single UART interface for monitoring. * *(**2:38**)* *Key Components:* * *AXI-Stream Snoop Ports:* Non-intrusive interfaces that allow observation of data on the AXI-Stream bus without affecting data flow. * *FIFOs (First-In, First-Out):* Buffers used to store incoming data packets from each of the four input AXI-Stream interfaces. * *Arbiter:* Logic that manages the selection and prioritization of data from the different FIFOs to send to the UART output. * *State Machine:* Controls the overall operation of the arbiter, with states like IDLE and WRITING, ensuring data is transmitted in complete packets. * *(**2:38**)* *Arbiter Logic:* The arbiter employs a priority scheme to choose which FIFO's data to send out first. In this example, FIFO 0 has the highest priority and FIFO 3 has the lowest. * *(**2:38**)* *Data Flow:* Data comes in through four AXI-Stream Snoop Ports, is stored in individual FIFOs, then the arbiter selects which FIFO to read from based on priority and data availability, finally outputting that data to a UART for debugging. * *(**6:11**)* *Important Concepts:* The video emphasizes understanding: * *AXI-Stream Handshaking:* The use of 'ready' and 'valid' signals for data transfer. * *Synchronous and Asynchronous Logic:* Different types of logic and their importance in FPGA design, especially for state machines. * *Packet Integrity:* Ensuring complete data packets are transferred without interruption. Summarized by AI model: gemini-1.5-pro-exp-0801 Cost (if I didn't use the free tier): $0.0675 Input tokens: 16454 Output tokens: 941
Loved this video stacey! Your way of looking at systemverilog and why we use certain constructs in certain way, is amazing, easy to understand and remember too. Thanks a ton....😇
Lovely video! you're the best when it comes to FPGAs! Can you make a video about Dynamic Function Exchange (Partial Reconfiguration) please?
Hello Stacey, Hello FPGA devs, i have a GOWIN Tang Nano 1K , on board it is equipped with crystal oscillator that outputs 27MHz as clock frequency. my question is: is that 27 MHz is "exactly" 27000000 Hz ?, or it's something closer if you know what i mean ,,,,,, i dont have an oscilloscope to test the purity of that 27MHz
Hi, www.youtube.com/@FPGAsforBeginners, In the advance level of out assignment, I think there should be some correction, If we follow the above examples. According to me it should be written as "assign out[(NUM_BYTE-i +1)*BYTE_SIZE-1 -:BYTE_SIZE] = in[(i*BYTE_SIZE)-1 -: BYTE_SIZE]". Please correct me if I am wrong! It might be correct If we ignore the previous examples :)
I have some problems. Can I use this design with Vivado 2018.2 Stacey ?
I didn't know about this new series ! As an embedded engineer (not fpga, more MCU, MPU) they get me a feel for the field! Thanks Stacey
Nice work Stacey!
Wow, this is super helpful, you really simplified it down, thanks!
Hello ma'am, the website is not responding ...... please help!!
You connect your peripherals to the interconnect_aresetn, when the Processor System Reset has a dedicated output called peripheral_aresetn. Is this going to be a problem? The instinct tells us that there are differences between these two resets generated by the reset IP. What can you tell us about that? Thanks!
There is a slight delay, as far as I know, between the peripheral reset and the interconnect reset. So that the interconnects can come out of reset first. However, unless your peripheral specifically needs this reset timing, it doesn't really matter in practice which is connected.
Thanks Stacey!
good
thanks to start posting video after long time
Hi Stacey what sort of throughput could you get? I am thinking of using ethernet RMII between an FPGA and a SOC without using a PHY.
Great Job Stacey...
Great job, Stacey. You do it very well. It pleases me that women also choose to geek out in these fields. I wish you all the best.
yeay ! )
Great Stacey! Stacey I just wanna ask: I currently code in VHDL as I find it very intuitive and engaging. I see you use verilog and system verilog most of the time. Is verilog (system verilog) easier to use in HDL design than VHDL or what is your reason for your choice of HDL? Thanks.
sv is now leading lang in industry
Yes, I have used VHDL for many years, but in recent years, I have gradually switched to Verilog because more and more of my customers are also switching to/using Verilog. That's why I recommend junior engineers start learning Verilog instead of VDHL.
System Verilog is better than Verilog and adds some of the neat features in VHDL such as structures.
@@cccmmm1234 Agreed
It awsome that you’re helping so much to open source FPGA design. I remember when I first started designing circuit boards and having great tools and recourses to learn from. Your videos are gonna be my goto now that I’m trying learn about FPGAs 😁
Top news! Well done!
Really nice, thank you very much
As usual, very useful video. Thank you. is there any chance that you can use one ETH IP with Zynq? and show us the source code for the ETH configuration. Also, PCIe is very common these days. you could use it with ZYNQ as well. Thank you so much for your videos