*Summary* - Stacey is continuing her Zinc series on RUclips; this is part three. - The video focuses on adding custom logic to a Vivado block diagram. - The current block diagram has wrapper files that forward internal signals. - Stacey plans to add her own top-level code to include both modules (existing and new). - She walks through the process of creating external and internal signals. - External signals are for communication with the outside world. - Internal signals are for interfacing with the existing block diagram. - She also sets up clock and reset signals, specifying that the clock is supplied by a processor already in the block diagram. - Stacey modifies a block RAM port to create a dual port RAM. - She has pre-written code that she adds to the project, specifically for generating Fibonacci numbers. - This code writes a new Fibonacci number to block RAM every half a second. - After adding the code, Stacey exports the hardware and switches to Vitis. - In Vitis, she updates the hardware specification and rebuilds the application. - She tests the existing code on her hardware to confirm it still works. - Stacey then modifies her code to read from the block RAM every second and expects to see new Fibonacci numbers in her debug output. The video serves as a comprehensive guide for adding custom logic to an FPGA project using AMD Vivado and AMD Vitis. It covers creating signals, updating hardware specifications, and modifying code.
Excellent presentation. The diagram in the beginning was really helpful to illustrate the process flow. Keep up the good work, this is very valuable for the uninitiated.
I appreciate your thorough and indepth tutorials for such a niche subject. I really enjoy FPGA and HDL but unfortunately it's quite hard to have a hobby in such a niche field without working in it.
Hey Stacey, thanks much for your Zynq series. If you could go on with an AXI stream slave interface - e.g. for reading data from an ADC - that would be terrific! Thanks again for the superb YT videos. Regards from Germany, Frank
Yes this would be great. Would be also interesting to see a streaming interface. Another interesting project would be a data capture IP in the PL which stores data (in BRAM?) provided for example from an ADC and sends this data array to the PS with the help of an interrupt. still dreaming of such an example ;) BTW: You made the best videos for Vivado/Vitis for beginners I have seen so far! great job
LOLZ I wish I had seen this sooner. I switched from an inferred BRAM of some struct to the block diagram BRAM, and my addressing seemed weird. First hint was the BRAM had a 4 bit write enable port and 32 bit address, but it took me 30 minutes to work out the BRAM wanted a byte address and not a word index. Seeing your excellent videos would have saved me a tonne of time Also, thanks for the intro to the board tab. No idea how I missed it before
You have no idea how long I struggled with the same thing when I was working on this video! I couldn't figure out why my addressing was messed up. I made the mistake too!
Hi, Stacey! I just finished trying this in Vivado + Vitas v 2024.1.1 and it seems that the two sides of the BRAM are not connecting to each other. Any ideas of how to debug it? Thanks!
Can you help me create axi transactions to write to fpga. I have everything ready. I connect clocking wizard, processor system reset, jtag axi, and my own ip core. When I run simulation everything is working fine. Also when I send write transactions it confirms the write data but when I read my data it reads zeros and not the result I expect.
Thank you very much for the helpful video. Please, I have a question; I have ZYBO_7Z010CLG400 board, I use its BRAM to save 8100 Byte (byte width). The report of resources utilzation is: 60 available 8 used 13.33 % I dont understand what (8 used) mean? I want to save more than 8100 byte but I cant.
Hi, great videos. I did the fibonacci project. And I see the number changes once per second. In your example, it's twice per second. When I check Vivado project, I see that FCLK is set to 50 MHz and in fibonacci verilog, I see localparam CLK_MHZ = 100; ==> Is that the root cause of my problem? It should be CLK_MHZ = 50 ?
First thing first , this channel is awesome.......... I just want to know about the FPGA because need to design ( just design) a CPU and my own game console. and where to start my CPU design journey?
These three Zynq series are quite useful but they are good only for people who already have some experience with the device and the tool not for the beginners. It is also presented too fast. Please go slower in your next videos and present it with more explanations. Also having your face video is distracting especially when you have to move it from right to left and left to right, either omit it or make it much smaller. I think adding an XADC block to your design for the next video clip would be a very helpful topic. Overall, a great work!
![Quando Rondo - Life Goes On [Official Music Video]](http://i.ytimg.com/vi/eIf3fhMXAow/mqdefault.jpg)
*Summary*
- Stacey is continuing her Zinc series on RUclips; this is part three.
- The video focuses on adding custom logic to a Vivado block diagram.
- The current block diagram has wrapper files that forward internal signals.
- Stacey plans to add her own top-level code to include both modules (existing and new).
- She walks through the process of creating external and internal signals.
- External signals are for communication with the outside world.
- Internal signals are for interfacing with the existing block diagram.
- She also sets up clock and reset signals, specifying that the clock is supplied by a processor already in the block diagram.
- Stacey modifies a block RAM port to create a dual port RAM.
- She has pre-written code that she adds to the project, specifically for generating Fibonacci numbers.
- This code writes a new Fibonacci number to block RAM every half a second.
- After adding the code, Stacey exports the hardware and switches to Vitis.
- In Vitis, she updates the hardware specification and rebuilds the application.
- She tests the existing code on her hardware to confirm it still works.
- Stacey then modifies her code to read from the block RAM every second and expects to see new Fibonacci numbers in her debug output.
The video serves as a comprehensive guide for adding custom logic to
an FPGA project using AMD Vivado and AMD Vitis. It covers creating
signals, updating hardware specifications, and modifying code.
You are the best!!!! Thank you so much. I understood how to link the PS and PL. I did in my Cora Z7 board.
Excellent presentation. The diagram in the beginning was really helpful to illustrate the process flow. Keep up the good work, this is very valuable for the uninitiated.
Glad it was helpful!
I appreciate your thorough and indepth tutorials for such a niche subject.
I really enjoy FPGA and HDL but unfortunately it's quite hard to have a hobby in such a niche field without working in it.
It is difficult. I also just learned about makerchip.com which looks really cool and useful.
Hey Stacey, thanks much for your Zynq series. If you could go on with an AXI stream slave interface - e.g. for reading data from an ADC - that would be terrific! Thanks again for the superb YT videos. Regards from Germany, Frank
Yes this would be great. Would be also interesting to see a streaming interface. Another interesting project would be a data capture IP in the PL which stores data (in BRAM?) provided for example from an ADC and sends this data array to the PS with the help of an interrupt. still dreaming of such an example ;) BTW: You made the best videos for Vivado/Vitis for beginners I have seen so far! great job
LOLZ I wish I had seen this sooner. I switched from an inferred BRAM of some struct to the block diagram BRAM, and my addressing seemed weird. First hint was the BRAM had a 4 bit write enable port and 32 bit address, but it took me 30 minutes to work out the BRAM wanted a byte address and not a word index. Seeing your excellent videos would have saved me a tonne of time
Also, thanks for the intro to the board tab. No idea how I missed it before
You have no idea how long I struggled with the same thing when I was working on this video! I couldn't figure out why my addressing was messed up. I made the mistake too!
Nice overview - this really helps, thank you so much for putting these videos out there.
You're welcome!
Hi, Stacey! I just finished trying this in Vivado + Vitas v 2024.1.1 and it seems that the two sides of the BRAM are not connecting to each other. Any ideas of how to debug it?
Thanks!
Really instructive videos
Thank you!! It's really helpful!
It's really helpful for beginner like me. Have you implement that neural network on fpga. Thanks
can you suggest me that, to which pin the external clock source of my created block design is to be connected in zc706 board ..?
Can you help me create axi transactions to write to fpga. I have everything ready. I connect clocking wizard, processor system reset, jtag axi, and my own ip core. When I run simulation everything is working fine. Also when I send write transactions it confirms the write data but when I read my data it reads zeros and not the result I expect.
Thank you very much for the helpful video.
Please, I have a question;
I have ZYBO_7Z010CLG400 board, I use its BRAM to save 8100 Byte (byte width).
The report of resources utilzation is:
60 available
8 used
13.33 %
I dont understand what (8 used) mean? I want to save more than 8100 byte but I cant.
thanks for sharing, my program build fine, But it does not show the text, data, bss ,dec values, so I can not see my elf size! what's missing there?
There are a couple of different log tabs, you may have to scroll or check them. Or see if there's any errors/warnings that are occurring at that step.
Hello Stacey , can you do a part 4 where you will try to use linux project in vitis instead of standalone project?
Hi, great videos. I did the fibonacci project. And I see the number changes once per second. In your example, it's twice per second. When I check Vivado project, I see that FCLK is set to 50 MHz and in fibonacci verilog, I see localparam CLK_MHZ = 100; ==> Is that the root cause of my problem? It should be CLK_MHZ = 50 ?
First thing first , this channel is awesome.......... I just want to know about the FPGA because need to design ( just design) a CPU and my own game console. and where to start my CPU design journey?
Thanks! and see www.edx.org/learn/design/the-linux-foundation-building-a-risc-v-cpu-core
@@FPGAsforBeginners thanks a lot
Can you do a tutorial about how to use TCP communication to transfer data in Zynq ?? Pleasee
If you are running this in Linux then it is a general Linux networking question. Thousands of examples available.
hello maam, can you please make a video of how to use qspi ip in vivado to connect external adc
Id like a one on one tutorial. Possible?
These three Zynq series are quite useful but they are good only for people who already have some experience with the device and the tool not for the beginners. It is also presented too fast. Please go slower in your next videos and present it with more explanations. Also having your face video is distracting especially when you have to move it from right to left and left to right, either omit it or make it much smaller. I think adding an XADC block to your design for the next video clip would be a very helpful topic. Overall, a great work!
promo sm 😆