Zynq Part 1: Vivado block diagram (no Verilog/VHDL necessary!)
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- Опубликовано: 24 авг 2024
- Hi, I'm Stacey, and in this video I show the vivado side of a basic Zynq project with no VHDL/Verilog required.
Not Sponsored, I just use this software a lot!
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Finally, a tutoral on Xilinix SoC's that makes sense.
This material was presented as only someone who really understands what they are doing can. I was especially impressed at how Stacey anticipated virtually all of the questions I had. Great job!
I absolutely love how involved you are throughout. Amazing.
The most clear and detailed explanation I've seen for a long time.
Glad it helped!
Thank you for this class. What incredible and detailed teaching, besides being straight to the point. It's hard to find good content on this type of subject; I really hope you continue sharing this kind of knowledge that ends up helping many people. Hugs from Brazil.
This is the first video in which I really understood what the teacher is teaching...
Thank you... Awsm video...
Really amazed to see how simple you made this topic for a beginner like me to understand. Thanks for the video. Looking forward to more such video tutorials!
Many thanks for your efforts Stacey. Your videos are very useful and we really appreciate your time.
Okay, this is weird - I was looking at Zynq SoCs only a couple of hours ago for a future project. I've used Vivado a fair amount when working with Artix-7s but never Vitis, so I look forward to part 2. Thank-you for your video.
This is the channel what i need! Thanks for share this content. Greetings from Argentina
Thank you, very helpful.
Stacey, you are a legend!
Excellent Vid & Explanation of this complicated Software & Project. Keep up the good work Stacey! 😁I've just bought a Zybo Z7-10 purely on the strentgh of this Vid!
Thanks for the nice video tutorial. Waiting for the next part.
Great video, always liked Vivado more than Quartus, much easier to learn
Thank you for the series.
Could you please make a video on some applications such as connecting camera, servo, dc motors, some sensors and etc?
Great video 👍👍👍
well done!
a stacey plus vivado. i like it
Great to see your new post Katy.
very clear and easy to understand, thanks!
I guess, those of us who don't have Zynq can use a microblaze for "processing system". I train on a board with a xcku15p-ffve1517. IMHO, the GPIO even doesn't need 4k range - 128 bytes looks sufficient. Are there considerations to put it bigger (like faster address decode, etc) ?
Thank you very much Stacey for this nice tutorial. I followed your 2 parts using Vivado 2023.2, but after using the exported XSA file in Vitis, there is no driver for block ram, I am able to use GPIO but the platform created has no driver for xbram. Either Vivado 2023.2 does not include it in the XSA file, or the Vitis software has a bug and can't see it in XSA file. I would like some advice on this
Useful example, thank you
Thank you for such a great video!
Great video! I've been struggling a lot with programming FPGAs for my master thesis and your videos have by far been of the greatest help.
One question about the peripherals: the way I understand the block diagram now is that the AXI interconnect is connected to both the LEDs and switches in this case, not the other way around. So, in this case, can the switches be used in this case to provide input back through the interconnect to the PS to make the LEDs turn on for example? Basically, is the master and slave AXI connection a two way street?
Yup, precisely! Actually in the Vitis video, I'll show how I connect the switches to the LEDs to do just that.
The question you asked has 2 components…
#1 as stacey replied to already… yes you can trigger interrupts on gpio input change to notify the zynq processor
BUT YOU ALSO ASKED “is axi a two way street” which is an entirely different question…
#2 Is axi a 2 way street? No… only the master can issue read write requests from peripherals!
Hi Stacey, can you please briefly explain the pin connection of FPGA board with laptop. I have USB blaster with JTAG. thanks
Thanks so much!
When do we use Constraint files?
great explanation. i am from india and i really enjoy your tutotial for block design but what we basically trying to do here ? turning on or off led through zunq processor or something else ?
Can you explain the mceliece cryptography system on vivado
thanks for sharing!
You're welcome!
You connect your peripherals to the interconnect_aresetn, when the Processor System Reset has a dedicated output called peripheral_aresetn. Is this going to be a problem? The instinct tells us that there are differences between these two resets generated by the reset IP. What can you tell us about that? Thanks!
There is a slight delay, as far as I know, between the peripheral reset and the interconnect reset. So that the interconnects can come out of reset first. However, unless your peripheral specifically needs this reset timing, it doesn't really matter in practice which is connected.
Thank you!
Omg where were you hiding till now