Great video on a very useful/must know FPGA topic. I will say I prefer to use the mark_debug attributes and then set up the from the set up debug option in the synthesis menu. Then i don't have to set up another IP
I think both methods have their place. I find this one easier to learn because you just treat it like any other IP core, and it also remains there from build to build, so it's easy to iterate on.
I have a Problem with my ILA. I am designing a Mircoblaze Softcore on an Artix-7 FPGA. I am using some external peripheral, some VHDL, to process these Signals. In the Simulation, everything is fine. But not in reality . Now I implemented an ILA in My Block Diagram, configured the IP-Core, but when I Program the FPGA over Vitis the ILA is not showing up. When I simply use the Bitsteam file it shows up.
I want to ask a different question. I have a zynq customized board which I am booting from sd card. I can also boot from qspi. There is a prebuilt bit file and ltx files for testing of PL section. When these files are programmed in zynq soc no ila core runs and nothing pops up. The error on tcl console says theere is no debug core in the programmed device. What's missing?
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Great video on a very useful/must know FPGA topic.
I will say I prefer to use the mark_debug attributes and then set up the from the set up debug option in the synthesis menu. Then i don't have to set up another IP
I think both methods have their place. I find this one easier to learn because you just treat it like any other IP core, and it also remains there from build to build, so it's easy to iterate on.
Very bright explanation! Please keep posting valuable videos 🙌
Yay more videos!!!
Very helpful, thanks!
Thanks a lot!
Thanks for the video!
I am trying to debug with ILA full quad spi bus. I right+click the spi bus external signal but I don't see 'debug'. Any idea?
I have a Problem with my ILA.
I am designing a Mircoblaze Softcore on an Artix-7 FPGA. I am using some external peripheral, some VHDL, to process these Signals. In the Simulation, everything is fine. But not in reality . Now I implemented an ILA in My Block Diagram, configured the IP-Core, but when I Program the FPGA over Vitis the ILA is not showing up. When I simply use the Bitsteam file it shows up.
I want to ask a different question. I have a zynq customized board which I am booting from sd card. I can also boot from qspi. There is a prebuilt bit file and ltx files for testing of PL section. When these files are programmed in zynq soc no ila core runs and nothing pops up. The error on tcl console says theere is no debug core in the programmed device. What's missing?