Reading from and writing to file: My PDM testbench from start to finish.

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  • Опубликовано: 15 сен 2024

Комментарии • 13

  • @FPGAsforBeginners
    @FPGAsforBeginners  Год назад +2

    Hi Everyone! Here's the github code for this project: github.com/HDLForBeginners/Examples/tree/main/30092022_testbench_start_finish And here's a playlist to the whole DSP series: ruclips.net/video/bI2O2JD9Ov0/видео.html

  • @thomasredden3159
    @thomasredden3159 Год назад +1

    Amazing!! I was just trying to figure out how to simulate input data for my project, and you have streamlined my research. Thank you!!

  • @yummypaint-uy6ze
    @yummypaint-uy6ze Год назад +3

    Wish i had these videos 10 years ago

  • @ΝικΝοκ
    @ΝικΝοκ Год назад

    Hello, i am relatively new to the fpga programming. I have bought an fpga from gowin (tang primer 20k since it was cheaper than others intel or amd chips). I figured out that files like time constraint files are a bit different. It would be great to do some basic videos demostrating some projects in other fpga brands too. Thanks alot

  • @MrVerilog
    @MrVerilog Год назад

    Another thing to do that is very useful is have an ifdef statement to select either data from a file or constrained random data to go into your "scan_file". Use a "+define+" in your vlog statement to select what you want. I also define the file I want to use using a +define+ and whether I want data from a file or constrained random data with +define+FILE_MODE
    Example for selecting constrained random mode: vlog -sv +define+MAX_DATA=1000 +define+MY_TEST_FILE="../sim_files/file333.combined.txt" test_tb.sv
    Example for selecting file mode: vlog -sv +define+FILE_MODE +define+MAX_DATA=1000 +define+MY_TEST_FILE="../sim_files/file333.combined.txt" test_tb.sv
    or something similar

  • @nanduthebond008
    @nanduthebond008 Год назад +1

    Hey Stacey, I recently joined as a graduate design engineer and your videos are super helpful! Could you add cocotb in your list of future videos please?

  • @LUCKYLUCKY-rs5ps
    @LUCKYLUCKY-rs5ps Год назад

    Hey sir / mam
    I name is lucky
    I need help regarding my work on a project on which i am working i don't know to to write a code of path planning in v hdl will u pls help me in this

  • @rafilyousif5324
    @rafilyousif5324 Год назад

    Hi Stacy!
    I have the Nexys A7 100T, and I am trying to program the onboard PDM microphone to output a 1 or 0 depending on if the input audio is a certain amount of decibels. I've never worked with the microphone, so is there anything you can do to help me out? I would really appreciate it.

  • @babatundetaiwo2817
    @babatundetaiwo2817 Год назад

    Hey how are you? I notice you have a lot of Verilog content. Any VHDL content?

  • @HalfLife2Beta
    @HalfLife2Beta Год назад +1

    Whats the best tool for simulation : cocotb or myhdl ?

    • @FPGAsforBeginners
      @FPGAsforBeginners  Год назад

      I haven't used myhdl so I can't say, but I do think cocotb is great.

    • @HalfLife2Beta
      @HalfLife2Beta Год назад

      @@FPGAsforBeginners please try myhdl :)