Hi Everyone, here's my latest video! I'm currently trying out early access on reddit! If you wanna see videos early before everyone else, go join the subreddit! www.reddit.com/r/HDLForBeginners I'm going to be doing the timing report and fixing the timing for this in the next video.
Hello.. Thanks for the video✌️. You said it will work in simulation but not in hardware.. Actually I am also trying to find logarithmic value of a number which can be fractional. I wanted to know how to represent a fixed point fractional number such that it is hardware implementable. Also can you explain us how to perform fixed point to floating point number conversation which is hardware implementable. And yes, please make video on signal processing block. I am also looking for a way to implement DFT on FPGA. I am working on project for hardware implementation of signal processing blocks, the all the things that you mentioned to cover in the series, would be really helpful to me...
At 9:50 I think you have an error on your overflow check comment. Instead of overflow = b2_coeff_f[B2_INT_BITS-1:B_INT_BITS-1] > 0 ? 1 : 0; Your range for b_coeff_f should be [B2_INT_BITS-1:B_INT_BITS]. The reason is that B_INT_BITS-1 is a valid bit b_coeff_f.
Hi Everyone, here's my latest video! I'm currently trying out early access on reddit! If you wanna see videos early before everyone else, go join the subreddit! www.reddit.com/r/HDLForBeginners
I'm going to be doing the timing report and fixing the timing for this in the next video.
Here I was struggling with this on my own. If I had only thought about this channel earlier, it would have saved me hours!
Thanks for the fixed point explanation. The excel illustration is really easy to understand.
Great explanation of negative bit slicing!
Thanks!
Love your channel! please make a video on signed fixed point multiplication :)
Awesome vid!
Looks Interesting !! I want to know is this method is the only way for fixed Point ?
great video. Maybe put "Part1" "Part2" etc on every video which is based on the previous ones.
Hello.. Thanks for the video✌️. You said it will work in simulation but not in hardware.. Actually I am also trying to find logarithmic value of a number which can be fractional. I wanted to know how to represent a fixed point fractional number such that it is hardware implementable. Also can you explain us how to perform fixed point to floating point number conversation which is hardware implementable. And yes, please make video on signal processing block. I am also looking for a way to implement DFT on FPGA. I am working on project for hardware implementation of signal processing blocks, the all the things that you mentioned to cover in the series, would be really helpful to me...
At 9:50 I think you have an error on your overflow check comment. Instead of overflow = b2_coeff_f[B2_INT_BITS-1:B_INT_BITS-1] > 0 ? 1 : 0; Your range for b_coeff_f should be [B2_INT_BITS-1:B_INT_BITS]. The reason is that B_INT_BITS-1 is a valid bit b_coeff_f.
Please make one clip on how to write an algorithm (like in previous video you said in algorithm on fpga) in hdl.
The algorithm code starts at 6:50 in this video in case you missed it, the next one will have registers included:)
@@FPGAsforBeginners yeah 🤟