Intel Quartus: Connecting Modules in Verilog

Using wires in Verilog to connect modules.
Tutorial by Tyler Kehne for Notre Dame CSE 20221 Digital Logic Design.

[@johnrex5342]

This is the best explanation I've seen on RUclips.

[@thebullybuffalo]

Bruh why would you make the ports the same name? So unecessarily confusing

[@fakehesap9365]

thanks Jay you are the best

[@emigdioalaniz]

you have more files on how to do modules or any book to use ??/

[@kevinsarmiento4275]

youre my goat

[@3liam7md123]

you're the best!!

[@TooSlowTube]

Do names in a module inside another module always have to start with a dot?
Is that the only situation where a name starts with a dot?

[@gabrielladangler1722]

From how I understand it, if you are using explicit declarations, then yes. I believe it means that the value should be referenced from the original module from which the instantiation is made. For example, the ".a" above pulls in the declaration of "a" from the module "myAND" and assigns it to the input declared in the current module, "input a". I hope this makes sense!

[@TooSlowTube]

@@gabrielladangler1722 Thanks.

[@M4DA.]

Thans Jay, very helpful ;)

[@CuongNguyen-id1ob]

Thanks so much for this useful tutorial!

[@fakehesap9365]

sen var ya adamsın