Lecture 15: Connectivity of Multiple Modules in Verilog

[@arunam6825]

EXCELLENT

[@riscvtransistors2ai]

Thanks

[@athuldas44]

Sir jaise jaise circuit banata hun mujhe module has been already declared error aa rahj hai 😢 main kaise solve karun

[@riscvtransistors2ai]

the possible error can be that you have already define include module command in multiple files. you only have to write that command in the top file