How to use vivado for Beginners | Verilog code | Testbench | Schematic View

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  • Опубликовано: 4 фев 2025

Комментарии • 94

  • @anandrajofficial1
    @anandrajofficial1  3 года назад +6

    Plz Help to reach 5K subscriber 🙏

    • @ArjunNarula1122
      @ArjunNarula1122 3 года назад +1

      ruclips.net/video/pTk1H50e8bI/видео.html

  • @ArjunNarula1122
    @ArjunNarula1122 3 года назад +5

    Verilog projects playlist
    ruclips.net/p/PLUn6cqainH8jZxS3ppSGPi3rNScz9cFZf

  • @abdxlive
    @abdxlive 4 дня назад +2

    Thanks Sir

  • @moviesera5250
    @moviesera5250 3 года назад +4

    Thanks my brother becoz of u i understood clear picture of using vivado I'm ur new subscriber

    • @anandrajofficial1
      @anandrajofficial1  3 года назад +1

      I am really very happy to hear this.
      Thank you for comment.
      Happy learning.

    • @moviesera5250
      @moviesera5250 3 года назад

      Bro I had some doubts in structural modelling can I get a video on it

    • @anandrajofficial1
      @anandrajofficial1  3 года назад

      @@moviesera5250 ruclips.net/video/6TS8dozKXBs/видео.html
      This xnor gate designed using nand gate in structural modelling design style.
      If u didn't understand plz do comment.

  • @kabandajamir9844
    @kabandajamir9844 Год назад +4

    So nice thanks crystal clear illustrations thanks

  • @balajis5170
    @balajis5170 2 года назад +6

    great video covering all basics

  • @PocketBrain961
    @PocketBrain961 4 месяца назад +2

    Мужик, не бросай, все получится

  • @racram0444
    @racram0444 Год назад +2

    Thank you for this :)

  • @Jhon0034
    @Jhon0034 3 года назад +4

    ty for this job

  • @mdfaizan1887
    @mdfaizan1887 Год назад +1

    Nice video ! this helped me a lot

  • @GlobalStreams
    @GlobalStreams 3 месяца назад +1

    Thankyou , it was helpful💌. While writing test bench why did you use $stop and not $finish?

    • @anandrajofficial1
      @anandrajofficial1  2 месяца назад

      ​@@GlobalStreams it's simple try both case in code ,you will see effect. Google it
      You can use $finish also.

  • @riyazbajishaik1596
    @riyazbajishaik1596 Год назад +2

    Thanks for the video sir.
    Sir, When I run the simulation it is taking forever.
    It is basically stuck in run. Do you have any idea about this?

    • @anandrajofficial1
      @anandrajofficial1  Год назад

      In test bench plz give $finish();
      Before endmodule

    • @riyazbajishaik1596
      @riyazbajishaik1596 Год назад +1

      @@anandrajofficial1
      Sir, Thanks for the quick reply.
      I did not include the test bench code.
      I was thinking of giving inputs through the available Force constant option after running the simulation.

    • @anandrajofficial1
      @anandrajofficial1  Год назад

      @@riyazbajishaik1596 then i think you have to stop simulation intentionally

  • @ylakshmichandra9181
    @ylakshmichandra9181 Год назад +1

    I have a "Xilinx ZYNQ XC7Z010" board, sir. I'm new to Verilog; which board should I choose under Boards in the software? I'm using the Vivado 2021.2 programme.

    • @anandrajofficial1
      @anandrajofficial1  Год назад

      During project creation it will give you option to select parts and board , select board and search for your FPGA board or after selecting parts you have to search for xc7z010. You will get it

  • @electroveda
    @electroveda 2 года назад +2

    Thanks

  • @zizo8737
    @zizo8737 3 года назад +2

    Brilliant

  • @mangapathiraju7198
    @mangapathiraju7198 3 года назад +1

    very nice...

  • @Nzx264
    @Nzx264 Год назад +1

    Sir after installing this , how much of space it occupied overall? I have only 80gb free disk space , can i download or not😢

    • @anandrajofficial1
      @anandrajofficial1  Год назад +1

      if you want to only simulate on device like zedboard or then 55-60gb but if u want to go for different series like ultrascale and plus then 75gb

    • @Nzx264
      @Nzx264 Год назад +1

      @@anandrajofficial1 it's just to learn the vivado tool recommended by my college is there any alternative tool to learn verilog with less memory is available? Pls show me some way!

    • @anandrajofficial1
      @anandrajofficial1  Год назад +1

      @@Nzx264 try vivado with lower version like 2017 below , and during installation don't select ultrascale , ultrascale plus and SoC device to reduce memory

    • @Nzx264
      @Nzx264 Год назад +1

      @@anandrajofficial1 ok sir thanks for replying

  • @caleb7799
    @caleb7799 Год назад

    Thanks for the easy to follow tutorial!

  • @nagasreevardhansharma722
    @nagasreevardhansharma722 2 года назад +1

    Sir is it applicable to 2022 version??
    Please 🙏 reply

  • @monsoonmallick9333
    @monsoonmallick9333 2 года назад +1

    Which edition of vivado is used ??

  • @_eye_killer_596_
    @_eye_killer_596_ Месяц назад

    Sir in vivado 2018.1 i cant generate simulation can you give me solution for this problem

    • @anandrajofficial1
      @anandrajofficial1  Месяц назад

      What error or issue it's coming?

    • @_eye_killer_596_
      @_eye_killer_596_ Месяц назад

      @anandrajofficial1 simulation runs very slowly it doesn't give output

  • @DAEC_ShreyaS
    @DAEC_ShreyaS 2 года назад +1

    While runing simulation in test bench I will get as invalid top module wt shld i do

  • @rookiegamer4657
    @rookiegamer4657 Год назад +1

    how to change font size in vivado text editor

    • @anandrajofficial1
      @anandrajofficial1  Год назад

      Go to Tools->Settings then popup will come.in left side Tool Settings option will be there. In Tool Settings->Text Editor then expand text editor ->Fonts and colors then see right left size option is there. Then as per your comfort increase size.
      In short
      Tools->Settings->Text Editor->Fonts and colors
      Then check top right side size option

  • @خفاش-ك7م
    @خفاش-ك7م 2 года назад +1

    thank you so much, I have a one question what is the purpose of clock ?

    • @anandrajofficial1
      @anandrajofficial1  2 года назад +1

      Cloçk in digital circuit used to synchronize the element so that it can work properly.

  • @lambroshalatsis6075
    @lambroshalatsis6075 2 года назад +1

    When I press schematic it opens a package window and a Device window and not a schematic window what do I do ?

    • @anandrajofficial1
      @anandrajofficial1  2 года назад

      it does not happened with me so i exactly can't say anything what is issues,plz search in google.you may find solution.

  • @menoxes1626
    @menoxes1626 Год назад +1

    does #10 mean wait for 10ns??

    • @anandrajofficial1
      @anandrajofficial1  Год назад

      No it's not wait time, it's like first test input will be generated at 0 time and will continue till next time, now as it 10 hence previous test vector will be till 10ns and continue till next time

  • @shanmukharaobudumuru4471
    @shanmukharaobudumuru4471 2 года назад

    Sir If we want to display something in xilinix using verilog code ( like just writing hello world ) where can we see the display output in xilinix

  • @anjalin7935
    @anjalin7935 3 года назад +1

    Hello it's taking too long to a create new project, is there any way I can fix it?? Kindly let me know if any..

    • @anandrajofficial1
      @anandrajofficial1  3 года назад +1

      Due to less RAM In pc,same happened with my pc too,.
      How much RAM ur pc have?
      If you want to do simulation only ,you can try with edaplayground.

    • @anjalin7935
      @anjalin7935 3 года назад +1

      @@anandrajofficial1 PC RAM is 8gb, actaully I needed to work on a project and I used to do small works on Icarus but I'll try once on edaplayground. Thank you!!

    • @anandrajofficial1
      @anandrajofficial1  3 года назад +1

      @@anjalin7935then it should work fine.for project vivado will be good.i don't know why it is slow in ur system.

  • @waelnour7147
    @waelnour7147 Год назад

    لو سمحت كلمة reg تظهر كلمة عادية وليست ملونة بالاحمر او الأزرق ؟!

  • @yashviya3698
    @yashviya3698 Год назад +1

    Sirrrr....I want link to download it....can u plss give...tommorow is my practical exam

    • @anandrajofficial1
      @anandrajofficial1  Год назад

      www.xilinx.com/support/download.html
      go to this link , select the version and then click on
      Xilinx Unified Installer 2022.2: Windows Self Extracting Web Installer . create account and then download

  • @debabratobanik2103
    @debabratobanik2103 3 года назад +1

    Which simulator is best and free for beginners for verilog hdl ??

    • @anandrajofficial1
      @anandrajofficial1  3 года назад

      Eda simulator and iverilog in my knowledge

    • @siddharthst2712
      @siddharthst2712 3 года назад

      u can use intel quartus prime lite with modelsim intel fpga starter edition , both of which are free

  • @maryamwaseem8633
    @maryamwaseem8633 Год назад +1

    Version kon sa hai? 14.7 ya 14.2

  • @VinayKumar-vi8bn
    @VinayKumar-vi8bn 2 года назад

    While adding source vivado stucking no matter what the time taking, how to add source pls give a solution

  • @pavanm6078
    @pavanm6078 2 года назад +1

    how can I change the font size here???

  • @valobhediya
    @valobhediya 3 года назад +1

    Can you please give me link to download this Xilinx Vivado please?

    • @anandrajofficial1
      @anandrajofficial1  3 года назад +1

      www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/vivado-design-tools/archive.html

  • @rsf2671
    @rsf2671 2 года назад

    Sir one verilog code for register.

  • @mihiram592
    @mihiram592 2 года назад +1

    Critical error message during simulation

    • @anandrajofficial1
      @anandrajofficial1  2 года назад

      I am not familiar with this error please search in google you may get soln

  • @kushalgourgonda3890
    @kushalgourgonda3890 6 месяцев назад

    Hiii sir please u can send me link 💕

  • @TravelandAdventure496
    @TravelandAdventure496 9 месяцев назад +1

    link please

  • @narsireddy_1
    @narsireddy_1 10 месяцев назад +1

    Link sir

  • @jeffrinwilfred1887
    @jeffrinwilfred1887 6 месяцев назад +1

    Thanks