How to Simulate a VHDL/Verilog code on Xilinx Vivado 2019.2

[@alanroberts1463]

Thanks Vipin, just what I needed. Very helpful.

[@VCodes]

Thank you!

[@DiywithElectra]

Thanks you so much... Very detailed explanation

[@VCodes]

You are most welcome

[@nandoperu100]

Thanks for explain the simulation function.. Good Job!!

[@VCodes]

Thank you!

[@nigarsultana6060]

Thank you. ..you explained every detail.

[@VCodes]

Thank you!

[@mamathakavati248]

Awesome for beginners, thank you for making this video

[@VCodes]

Thank you!

[@SAKTHITech]

Thank you so much!! Keep up the great work

[@VCodes]

Thank you!

[@sathissivaram4499]

how to eradicate launching error while simulation. Please clarify it.Thankyou

[@ashishanand9518]

that was very helpful vipin :)

[@tanchienhao]

worked for me, thanks!

[@VCodes]

Thank you!

[@TilankaDil]

Thank You very Much..Great Explanation...

[@VCodes]

Thank you!

[@nunustone7133]

Thx for this well prepared tutorial.

[@VCodes]

Glad it was helpful!

[@gayathrivenkatesan3958]

Very helpful..! Thanks :)

[@VCodes]

Thank you!

[@roshithbabu6845]

Thanks from the heart

[@VCodes]

Thank you from the heart as well...

[@felipeferreira1960]

Very helpful video

[@VCodes]

Glad to hear that

[@cristianlerro9570]

thank you for ur work, it is very useful!

[@VCodes]

thanks. glad to hear that it was helpful..

[@qwerty_____146]

Thank you Dear.

[@VCodes]

Thank you!

[@d7x2y]

Thank you Sir for making this good video. Since I have no physical board to test, do I need to code a workbench.vhd file as well in case of testing my own codes? THX

[@VCodes]

yes, its always recommended to write a testbench code and test the code before finalizing it. Otherwise how will we know if the code is working. Just getting it compiled without errors isnt enough. Even if you have the fpga board, I would first verify with testbench. Debugging on board, normally is more time consuming.

[@ashishmulajkar1986]

Thank you very much...I can apply this logic for my research work

[@VCodes]

Thank you!

[@kabandajamir9844]

So nice thanks

[@VCodes]

Thank you!

[@farzadrazmavar8012]

thank you so much

[@VCodes]

Thank you!

[@anubhavmondal6074]

Hey vipin i am using mac os but I need this software can you tell me any alternative of this software for macos ..

[@suvendusahu6628]

Nicely explained 👍👍

[@VCodes]

Thank you!

[@sokullumahmutpasa6651]

thanks

[@deathmaster4035]

How do you save the simulation results to a text file?

[@roshithbabu6845]

U r awesome

[@VCodes]

Thank you!

[@shivaramakrishna5078]

It Supports mobile ?

[@masmry2703]

Thanks Vipin

[@VCodes]

Thank you!

[@Az1kJ]

Where is verilog code?

[@pallavisingh7110]

Test bench code is not working, it shows 9 errors

[@VCodes]

What errors are you getting? Dont try to synthesis the testbench. Testbench is only for simulation.

[@mokadinesh2721]

hi can i use report statement in VHDL? in vivado

[@VCodes]

you can. I will write or publish something on this soon.

[@danny_racho]

Ehm why do you have the word "verilog" in the title, if it's just vhdl? This is absurd..

[@VCodes]

Thats deliberately put there because the steps involved in simulating a verilog code is not much different than vhdl. Did you try following the steps mentioned in the video?

[@thedude7134]

I need help with VHDL assignments. I'm willing to pay for tutoring as well... kindly reach out to me if you are interested. Thank you

[@VCodes]

I wasnt available for tutoring then. Now I have started doing so. Putting this out here for anyone who is interested. Thanks for the support.

[@brajkishorrajput9238]

plz share any contact detail sir

[@VCodes]

my email should be visible in the "about me" section or from my blog, vhdlguru.blogspot.com/

[@almostabouteverything1112]

Very helpful video

[@VCodes]

Thank you!