17 - Developing Simple Verilog Testbenches

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  • Опубликовано: 2 ноя 2024

Комментарии • 2

  • @drbalontotis2474
    @drbalontotis2474 Год назад +1

    you teach us very well 🤯

  • @amankumarpurohit3008
    @amankumarpurohit3008 Год назад

    When you changed signed decimal to unsigned decimal then why the overflow is asserted there??