Vivado Tutorial: Turn Verilog IP into AXI Module

[@mriosrivas]

This is what I was looking for. Thank you so much, I really appreciate your effort!

[@stevenalexander6262]

very nice, AXI is so new to me and I just wanted to use my newly made verilog code on my pynq, this helped tons

[@weiyizhang4317]

Hello, thank you for the lesson very much! I wonder is there any example which uses both input and output axi stream? Thanks a lot!

[@susmitamaloji7111]

How to create that twophase program in this video. If anyone know plz reply to this

[@MonishaK-sh9bk]

i want to know how to give my data into the IP, using SDK , please provide any video or documents

[@beccadls2838]

Didn’t understand a word of this but cool!

[@kirtikumarbaba]

it's useful thanks.!

[@iremnurcolak620]

Hello, what is IP? I was looking for AXI implementation but I came across IP in RUclips a lot. I do not know what it is actually. Thanks :)

[@clintlemire8741]

Intellectual Property. In this context, it is referring to your design.