This was a very good beginner's presentation to the PCI Express Physical Layer. This presentation has now given me the confidence to do some deep diving by checking additional literature on PCI Express. Thank you very much.
Very Good Presentation on PHY Layer for PCIe and learnt new things from your session Sir and requesting you that giving session on Transaction Layer and Data Link Layer also.
I was hoping you might explain how 128b/130b encoding could possibly maintain DC balance with disparity. Perhaps I am misunderstanding it but it seems that with 2 bit periods to compensate, it couldn't. I have the same question how all zeros could even be DC balanced with 8b/10b.
Thanks so much... So the Receiver does clock and data recovery on its Receiver block side from its Rx stream. What about PCIe Clock reference? Is it sync in both Driver and Receiver? OR separated ref clock on each side?
A PCIe device can choose to use the reference clock or it can provide its own. If it provides its own it has to be within the +/- spec (off the top of my head +/- 300 PPM). I suppose both TX and RX sides use the reference clock but I also suppose this is implementation specific!
Doesn't scrambling also help with DC balance and to ensure sufficient transition for clock and data recovery (in addition to 8b/10b) ? Is scrambling AND b8/10b used at the same time? In the FPGA based example, where is the scrambling done?
No, scrambling is used to spread out the frequency content in the signal, which lowers electromagnetic interference (EMI). 8b/10b encoding is used to embed the clock in the signal and to provide DC balance. They are normally used both at the same time but the scrambling can actually be disabled. Scrambling is also not enabled for the PCIe compliance pattern (which does use 8b/10b encoding).
This was a very good beginner's presentation to the PCI Express Physical Layer. This presentation has now given me the confidence to do some deep diving by checking additional literature on PCI Express. Thank you very much.
it's almost midnight on a Friday, and I'm learning about the physical layer technology of PCIe....
Doo Doo
Doo Doo
Doo Doo
Doo Doo Doo
Doo Doo
I hope you enjoy my rendition of your theme song.
John, this is an explanatory explanation! By watching this saves me a lot of time!!
Really enjoyed his presentation style which helped me to understand each concept well. Thank you!
That is an eye opening experience. Thanks for the video!
Very clear presentation! Thank you so much!
Great presentation. Thank you!
Really great video, thank you so much for the wonderful content!
Hi, That was an excellent video. Hope you release more and more such videos in the future
Very Good Presentation on PHY Layer for PCIe and learnt new things from your session Sir and requesting you that giving session on Transaction Layer and Data Link Layer also.
Video ends at about 44:15. After that its just a black screen until the end of the video.
Beautiful.. Thanks for sharing this with the world
Such a great presentation. Thank you! Much appreciated.
Excellent Presentation! Thanks alot!
can you provide the links to the video for Pcie communication packets
Excellent, please make more video.
Correction: 27:51, 400ps/bit Not 400ns.
Great stuff
Very clear explanation of PCIe. Thanks.
Awesome learn a lot from you!
Great training video.
Are you planning to cover other PCIe layers in same way?
42k views in 3 1/2 years. My faith in geekmanity is restored.
Very informative, thanks for sharing.
Thank you that was really helpful
I was hoping you might explain how 128b/130b encoding could possibly maintain DC balance with disparity. Perhaps I am misunderstanding it but it seems that with 2 bit periods to compensate, it couldn't. I have the same question how all zeros could even be DC balanced with 8b/10b.
Doo Doo
Doo Doo
Doo Doo
Doo Doo Doo
Doo Doo
I hope you enjoy my rendition of your theme song.
Thanks so much... So the Receiver does clock and data recovery on its Receiver block side from its Rx stream. What about PCIe Clock reference? Is it sync in both Driver and Receiver? OR separated ref clock on each side?
A PCIe device can choose to use the reference clock or it can provide its own. If it provides its own it has to be within the +/- spec (off the top of my head +/- 300 PPM). I suppose both TX and RX sides use the reference clock but I also suppose this is implementation specific!
Can anyone tell me how long is tens of inches stated at 22:30?
Thanks a lot.. It really very informative.. But have a doubt about usage of SKP data characters.. Can any one give some brief about there usage??
Doesn't scrambling also help with DC balance and to ensure sufficient transition for clock and data recovery (in addition to 8b/10b) ? Is scrambling AND b8/10b used at the same time? In the FPGA based example, where is the scrambling done?
No, scrambling is used to spread out the frequency content in the signal, which lowers electromagnetic interference (EMI). 8b/10b encoding is used to embed the clock in the signal and to provide DC balance. They are normally used both at the same time but the scrambling can actually be disabled. Scrambling is also not enabled for the PCIe compliance pattern (which does use 8b/10b encoding).
Thanks!
Right!! The 8b/10b dwords were made in such a way that the only valid combinations by which they can be sent are DC balanced (equal 1's and 0's).
what is the link for part 2 ?
Thank you.
like it. Thank you
Will watch again..maybe at 1.25 speed. I don't mean that in anyway but that I want to catch up.
Is there a link to the presentation ?
bookmark 31:25