PCIe Architecture: Lecture-1

This video explains the following in the PCIe Protocols
Introduction to PCIe Protocols
Concepts like lane, link, initialization, differential signal, throughput.
PCIe Topology, various components ( Root Complex, End Point ( Legacy End point, Native End Point), Switch etc.
PCIe architecture in terms of logical layers.
Three layers ( transaction layer, link layer and Physical layer).
Task of each layer
Logical Packet flow inside PCIe controller

[@naveen7282]

Very nice explanation. This lecture were telling on LinkedIn for 10k rupees.

[@prasadm8441]

Yes true

[@venkatasairam2283]

please tell me course name in linkedin

[@venkatasairam2283]

@@prasadm8441 please tell me course name in linkedin

[@ryanjohnson4565]

This is by far the best PCIe explanation I have come across

[@vipuljain6986]

Thanks Mr. Lovekesh for taking initiative to pass on the knowledge and saving lot of our time and keeping our attention focused during this entire Part.1 video of PCIe.
It was very good start for us and to gain enough confidence to start deep diving.

[@manognajohn1508]

Hi , I am working in VLSI industry. I got PCIE project today. fortunately, I got to know this video. now I got some understanding . Thank you so much.

[@gauravkumar-se9qs]

It's a really good video.

[@prashanthiprashu4211]

can you please explain what is address space , configuration space header types of transaction , what is memory mapped io space , configuration transactions, message transactions??

[@kalyansumankv]

One of the best lectures on PCIe. Thanks

[@Mr_ST_720]

Best explanation till now seen simple to complex clearly explained.. thanks so much

[@liamdillon3176]

Quality presination, as Naveen commented below, i have paid for PCIe training online and this is better.👍

[@108ahah]

Very good video. Hope to see more videos coming.

[@rajeshhariharan7575]

PCIe nicely explained for beginners... Thanks so much.

[@muhammadbilalmalik6684]

at 13:26 you are saying that if (ENDPOINT) EP3 has to communicate with EP2, it will go through switch. But I believe that both EPs CAN'T communicate like this, there should be proper transaction from RC(root complex) via core. If any communication has to happen between two EPs then 1st EP will write on certain MEMORY and other EP will read from that.
Please correct me if I am wrong.
Thanks

[@tiktikbadboy8586]

I am a new engineer and learning the PCIe switch. These are very good material to learn. Very thanks for your support. By the way, considering that you chose to use Notability for the presentation. How about you change to use Good Notes 5. There is a feature "Laster Pen" that allows you to point out something without really draw on your notes. Hope that helps.

[@pcie3823]

Thanks a lot for the suggestion. I will explore it.

[@kapilkhare6658]

waiting for next lecture on PCIe sir. Please upload soon sir. Want to learn enumaration, power manegment and link initialization concept.

[@pcie3823]

Thanks Kapil, I recorded next video just now and will be uploading soon.

[@pcie3823]

Hope, these videos are helpful.

[@prasadm8441]

@@pcie3823 very helpful sir. Could you please let us know have you recorded all concepts and upload anywhere. It would be fine even if it’s chargeable please update sir

[@livechristo]

Very good explanation in detail. Covered all sides of pcie

[@vishnupriya6246]

Hello sir. Very good lecture. Easy to understand the concepts. If u provide the PPT or notes with the video it will be very helpful.

[@aashris]

This is such a great video. Very clear explanation! Thanks so much! :)

[@AshokKumar-bf8mv]

Wonderful lecture sire,,, Thanks a lot..

[@subhamraysingh6715]

Hi Could please make a video for ltssm States it would be helpful for us

[@ramakrishnachintha9204]

some topic are missing like transport layer and data link layer and physical layer please upload this topic ........please

[@user-dd2pn1uj9k]

Very helpful lectures sir. ❤

[@Brigadorski]

In PCIe Version 1 on a x1 configuration, the maximum data transfer rate is 160 Gbps (2.5GT/s), but only 2 Gbps (250 MB/s) is encoded serial data?

[@arijitsarkar3551]

Short and helpful.

[@asana.abhyasi]

@PCIe sir, can we get the notes as well? btw, I am indebted to your for this valuable content delivery that too on free platform like youtube. thanks a lot. :)

[@vinayb4599]

Thank you sir, nice lecture...

[@lakshmi-kb4ww]

Grt explanation sir, thank you so much, if you can attach the slides or pdf which you were explaining would be helpful for us

[@nikhilreddy719]

Is the UPHY (universal physical layer) a part of PCIe controller? Aren't the PCIe controller and UPHY layers different?

[@akshaygodase8067]

Awesome! You have saved me! Thanks for this information

[@rahulsutar9042]

well explained thank you

[@Brigadorski]

In a single lane, how fast is the data speed? Can the Tx and Rx channels transmit data simultaneously at 2.5 GT/s? Or is the maximum transfer speed only capable on a single channel, Tx or Rx at a given time?

[@ShopperPlug]

Thank You for this lecture.

[@jyotigulati5624]

Excellent Video

[@muralikunapureddy8240]

Any details about the tutor ?? From college or industry ??

[@pcie3823]

Hi Murali, I am from Industry (Bangalore)
.

[@muralikunapureddy8240]

@@pcie3823 may I know your name ??

[@pcie3823]

@@muralikunapureddy8240 My name is Lovekesh Gupta

[@sandeepkulkarni4985]

Hi, Thanks for the detailed video. Can i get the document made by you while you were explaining this? It would be very helpful for us to read all information at one place.

[@DineshKumar-nt4dp]

Hi, Thanks for the video... well explained. I am working on PCIe IP at SoC level and I have topics to be clarified on pcie. is there any Linkedin/google groups available?? so that doubts can be discussed in detail. Thanks.

[@EngineerAnandu]

Pls upload more.

[@alannobakht8503]

WHat do you mean by "Meaningful 8-bit"?
8/10 bit Encoding is for scrambling, Clock Recovery and maintaining DC Balancing and in fact replacing each scrambled BYTE with 10-Bit code before sending the code on the link right after serializing it.

[@pcie3823]

When I say, Meaningful 8-bit, its from user( application layer) perspective. To transmit 8 bit over PCIe link (gen1 and gen2) , 10 bits have to be transmitted ( extra 2 bits are required for PCIe link to function properly as mentioned by you also), But these extra bits reduces the bandwidth to 80% of 2.5 Gb/5.0Gb (for Gen1/Gen2).Just to emphasize on this point, I used that for every 10 bits transmitted over link only 8 bits are meaningful ( for user).

[@darshansatyamurthy]

Would have loved to listen to basics of LTSSM states too.

[@krishnanshankarb]

very nice presentation ,...can we get your notes as a pdf or ppt?...Thanks a lot

[@friosminsysnym]

very nice

[@omkarsingh1093]

Hi, Thanks for sharing this video. Is it possible to share the docs you have prepared. Also how we are initialsing PCIE from software perspective. Really thank full to you.

[@baliparasantosh]

Sir, Can you please upload the document (note) you are using in the lecture. It will help to go through it in one go.

[@saishashelge9345]

Need some testcases on this

[@phanisai22]

Good Job sir, very nice explanation. could you please provide notes link which you prepared soft copy of this video, it will be more beneficial. Thank you very much

[@gosolotravelling]

Great boss. Thanks

[@saranyas304]

thank you for this video ..!!

[@srikantachaitanya6561]

Thank you very much .....

[@Carlosramirez-he4zi]

Thank so much !

[@huaxzhang]

If you type it in instead of write it up, your notes and diagrams would be more readable.

[@raghul1208]

thanks for this

[@suryatejakothakota7742]

x12 not supported by pcie

[@raghuramchary9119]

Can we please have the lecture in hindi too ? thanks for the video sir

[@potibundakay1664]

What is sideband signals...

[@poluajay7627]

Which pcie generation you took in this video sir ..

[@saivarun9677]

Can I please have your notes as a document for all 4 videos? I will help a lot.🙂

[@atifjaved81]

Hi can i receive these notes, Lecture is quite impressive

[@babajan6530]

Thanks

[@butterflySpirit717]

Thanks sir ..

[@mkanimozhi]

Can you share this PDF as quick reference

[@satishkumargupta1320]

hearty thanks :)

[@413sekharece]

Is it possible to share the slides ?

[@alihamidrezanobakhtirani1675]

summary & useful Bravo!

[@saishashelge9345]

Please help with that

[@venkatas3557]

Hi Can I get in touch with you ?

[@techspecialinformation7746]

Most boring lecture

[@ETSolutions]

very nice

[@ushapaayasam4326]

Thank you !!