Hi Sir, Can you please clarify the address alignment rule that you talk about at 12:40 please? Why can't we use the starting address at 0x8000_0000 for example? Why does it have to be 0XC0000000?
I don't know if you still need the response, but perhaps someone else might h sees this comment later. The way I understood it is in the following way. The start address of the block should be a multiple of the block size. You don't want to end up wth a 0x40001000 - 0x60001000. The reason for that is readability and memory management. I'm not quite sure though why he chose 0xC0000000 as an example for he offset of 2G.
It looks like I am a few years late, but thank you for this series!! I am in my third year of university and just purchased myself a Zybo Z7-20 to mess around with and develop my FPGA/embedded skills. The two videos I have watched have already provided invaluable information to me and I am looking forward to learning more from you.
@@MohammadSSadri Brother if possible can I have the lecture slides of your lectures. Actually I take print of lectures and note down your points on lectures. I prefer to have notes in hardform as it becomes easy to revise
want to learn how to design Xilinx FPGAs? join today to my udemy course: www.udemy.com/course/vivado-learn-from-the-beginning-and-with-pcie-full-project/?referralCode=35850E883A41A0FCECE8
Amazing video. Thanks for the great job! Very clear and very precise. PS: On the slide of the Hierarchical AXI Interconnects , the AXI slaves 1 , 2 and 3 should have a circle on their ports right ?
Hi I am just not understanding what you mean with this : 2G have to be allocated from memory address 0xC0000000 because, if I am right, from this address to 0xFFFFFFFF there is just 1G space. Do I am wrong? Why is that like this? Thanks in advance. Best regards
Sir,I had a question........AXI interconnects has register slices (or pipeline of registers) which increases latency between slave port to master port communication......but it increase clock frequency......it looks like at one side you are decreasing speed of communication(through latency) and another side u are increasing it(through clock speed).......Somewhere I am wrong in my basics.......please correct me!!!
Hi I began working with the ZYNQ from almost the beginning days that Xilinx released it. And that was my days of doing PhD at the group of Prof. Luca Benini of ETHZ. Those days we used the ZYNQ as a bridge for a 64 cores processor from ST micro-electronics.
Hi Mohammad, great video. Helped a lot. Quick very basic question. When you say an AXI bus, for example, is 32 bit wide does it mean each bit acts like a serial line?
+Sai Ganesh your system is not necessarily running on a single clock. for example you have a cpu which is running at 200mhz and a piece of logic which is running at 125mhz and these two guys need to be able to talk. that was a simple answer. as you make progress through your studies you will see that frequency scaling is one of the most effective tools for reducing power consumption of a device. there you will find out that every piece of your logic can run at a different clock frequency than others based on its temporal workload.
The smacking sound is so distracting that i stopped listening to the video after first couple of minutes. I appreciate you taking out time to create these video. Can you keep the mic at a distance from your mouth when you're talking.
+manav raina i know! sorry for that. this was actually my first first video. the rest are fine. or... the rest are better. i apologize for the sound quality in this one.
That is actually a good advice Eralp, I have learned to do this from my Maya teacher. I will try to stop doing that, but i don't promise ;) Since it is a kind of synchronization point in my mind... and thanks Poly for support.
Hi Sir,
Can you please clarify the address alignment rule that you talk about at 12:40 please? Why can't we use the starting address at 0x8000_0000 for example? Why does it have to be 0XC0000000?
I don't know if you still need the response, but perhaps someone else might h sees this comment later. The way I understood it is in the following way.
The start address of the block should be a multiple of the block size. You don't want to end up wth a 0x40001000 - 0x60001000. The reason for that is readability and memory management. I'm not quite sure though why he chose 0xC0000000 as an example for he offset of 2G.
It looks like I am a few years late, but thank you for this series!! I am in my third year of university and just purchased myself a Zybo Z7-20 to mess around with and develop my FPGA/embedded skills. The two videos I have watched have already provided invaluable information to me and I am looking forward to learning more from you.
It is never late.
@@MohammadSSadri Brother if possible can I have the lecture slides of your lectures. Actually I take print of lectures and note down your points on lectures. I prefer to have notes in hardform as it becomes easy to revise
Thank you, very clear explanation about the basics of AXI Interconnect blocks. It helps me understand Xilnx ZYNQ FPGA design.
YOU! Are a very good presenter. Thank you for putting up these videos :-)
want to learn how to design Xilinx FPGAs? join today to my udemy course: www.udemy.com/course/vivado-learn-from-the-beginning-and-with-pcie-full-project/?referralCode=35850E883A41A0FCECE8
Thanks! This video is very helpful to me. I always wondered that what's the purpose of AXI Interconnect. and this video was became answer.
Thanks for the great examples for each point you were trying to make. If only everything was explained like this :)
this series is really helpful..thanks for making them.
Hi, first of all thank you for these and the other series. Nice work! It was very helpfull to me!
regards
Amazing video. Thanks for the great job! Very clear and very precise.
PS: On the slide of the Hierarchical AXI Interconnects , the AXI slaves 1 , 2 and 3 should have a circle on their ports right ?
Hi. Thanks. Yes. Basically we use the circle to show the AXI Slave plug.
Hi I am just not understanding what you mean with this : 2G have to be allocated from memory address 0xC0000000 because, if I am right, from this address to 0xFFFFFFFF there is just 1G space. Do I am wrong? Why is that like this? Thanks in advance. Best regards
+hahahaha you are right. in the video please suppose that the required address range of axi slave 2 is 1G and not 2G.
+Mohammadsadegh Sadri Thanks for your quick answere! BR
or the offset could be 0x80000000 with the range 2G
Sir,I had a question........AXI interconnects has register slices (or pipeline of registers) which increases latency between slave port to master port communication......but it increase clock frequency......it looks like at one side you are decreasing speed of communication(through latency) and another side u are increasing it(through clock speed).......Somewhere I am wrong in my basics.......please correct me!!!
do you have any video about data transmission using ethernet? And let me finish this video series can I process data using ethernet?
Could you help me anyone how to write requirements for interconnect between processing system and programmeable logic?
Thanks for sharing Mohammad.
For how long have you been working with Zynq?
What kind of things have you been able to build?
Hi I began working with the ZYNQ from almost the beginning days that Xilinx released it. And that was my days of doing PhD at the group of Prof. Luca Benini of ETHZ. Those days we used the ZYNQ as a bridge for a 64 cores processor from ST micro-electronics.
How to interconnecte between PS to PL , how to write a requirements ?
Thx for the video but ....Are you eating in the same times?
:D dont remember what t...f... i was doing ... ;) maybe i should create a better version...
@@MohammadSSadri It is fine free content is always nice and I know how many effort /time it takes .
Hi Mohammad, great video. Helped a lot. Quick very basic question. When you say an AXI bus, for example, is 32 bit wide does it mean each bit acts like a serial line?
No, everything is parallel.
05:36 "decrease" the latency of data*
0xC0000000 is not a valid start address for 2G area, you need 31 bits so 0x80000000 is the first valid in your case.
Please tell me what is the advantage of having two different clocks ?
+Sai Ganesh your system is not necessarily running on a single clock. for example you have a cpu which is running at 200mhz and a piece of logic which is running at 125mhz and these two guys need to be able to talk.
that was a simple answer. as you make progress through your studies you will see that frequency scaling is one of the most effective tools for reducing power consumption of a device. there you will find out that every piece of your logic can run at a different clock frequency than others based on its temporal workload.
Alignment rule, che matlab darid?
It helps me a lot!!! Thank you very much!
Thank you sir , it helps to me a lot!
Hello sir IAM doing project on axi protocol in verilog can you help me please
how can i help you?
@@MohammadSSadri
Hello sir your tutorials are really good
Sir can you send me the rtl code of axi to my mail: malesaimhbd@gmail.com
@@MohammadSSadri
Sir please send the rtl file for this axi protocol
@@malesai3893 i have some videos regarding this topic on microelectronics reasearch group of tu kaiserslauter youtube channel. please watch them.
Thanks for making this videos
Great video, thanks !!!
Thanks for the video.
thanks again.
آقا دمت گرم کارت درسته
Thank you!
The smacking sound is so distracting that i stopped listening to the video after first couple of minutes. I appreciate you taking out time to create these video. Can you keep the mic at a distance from your mouth when you're talking.
+manav raina i know! sorry for that. this was actually my first first video. the rest are fine. or... the rest are better. i apologize for the sound quality in this one.
x1.25 speed is good for me
i will create a new version soon in which i speak faster. thanks for suggestion
Stop smacking sounds, geez.
Stop complaining for something that is given to you for free by someone that does it in his free time just so you can boost your learning curve, geez.
That is actually a good advice Eralp, I have learned to do this from my Maya teacher. I will try to stop doing that, but i don't promise ;) Since it is a kind of synchronization point in my mind... and thanks Poly for support.
Mohammadsadegh Sadri
I didn't notice this. I like your clear communication style.