TRM part description was absolutely fabulous. Actually, with understanding this part you are able to create your own system. Thank you very much dear Dr. Sadri for your effort to share your knowledge.
bees knees -- I'm sorry to hear that because this guy was boring the crap out of me in the first minutes. I know how a bus works generally, I know what a bus master is. Anybody who even just casually plays around with Zynx SoCs knows that. What I don't are AXI specifics, how to generate the AXI interface on the PL side and also work it from that side.
If you start finding this video confusing, jump to 37:00 for inspiration and the overview. I've tried reading UG585 on my own and it's rather daunting. This video made it easier to understand, even though it's still a bit confusing. Thank you!
want to learn how to design Xilinx FPGAs? join today to my udemy course: www.udemy.com/course/vivado-learn-from-the-beginning-and-with-pcie-full-project/?referralCode=35850E883A41A0FCECE8
You are a magician make difficult things easy. I really appreciate it!
TRM part description was absolutely fabulous. Actually, with understanding this part you are able to create your own system. Thank you very much dear Dr. Sadri for your effort to share your knowledge.
The pace is just right for my brain to keep up.
bees knees -- I'm sorry to hear that because this guy was boring the crap out of me in the first minutes. I know how a bus works generally, I know what a bus master is. Anybody who even just casually plays around with Zynx SoCs knows that. What I don't are AXI specifics, how to generate the AXI interface on the PL side and also work it from that side.
I watch each and each of your videos and they are really really helpful.
Great Video to Learn Zynq FPGA, Nice explanation and Dr. Mohammad has very good skills to explain in simpler manner.
If you start finding this video confusing, jump to 37:00 for inspiration and the overview.
I've tried reading UG585 on my own and it's rather daunting. This video made it easier to understand, even though it's still a bit confusing. Thank you!
thanks for videos, very good presentation and explanation
Wish I can watch all of them 3 years ago. Really good intuitive videos!
this lesson is what i need! Congratulations!!!
Very helpful Dr. Sadri. Thank you for making these wonderful videos
Shelden Cooper bro.. great lecture and good clarity.. Thanks a lot!!
You did a superb job with this, thanks.
This video is so useful! I really appreciate it
Very informative video, many thanks
This is indeed a Great Tutorial....!! Thanks a lot for posting this.!
want to learn how to design Xilinx FPGAs? join today to my udemy course: www.udemy.com/course/vivado-learn-from-the-beginning-and-with-pcie-full-project/?referralCode=35850E883A41A0FCECE8
At about 9:25 there is a mistake u said master sends ready signal but I think slave should be ready for data write.
Yes, you are correct. My fault. Thanks for the notation.
Why there is no read reasponse channel in axi ?
gooooooooooooood video
Thank you so much, its very helpfull
what ’s name the book？
24:51 System diagram
Dr.Mohamed Great thank for your help
Thank you for very helpful lecture
Thank you so much for your helpful lesson
Well done.
I love you
thanks a lot
9:07 who came in?
great thanks
Thank you
:D