sweet, thank you so much, I already thought I'd never find good introductory resources on FPGA developement! Hope you find the time to keep up with these tutorials!
Thank you for the video, you teach from basic ideas is very helpful. And the speed of your talk is very kind for non native English speaker. Thank you very much.
i was proceeding for SoC design and validation training and your videos provided more than a kick start! and your content was quite better than others like everything i wanted. Thanks and love from India
Nice video,but what is use of buying an FPGA if follow the protocol to communicate internal modules when practically it's works serially rather than we bought FPGA to develop working things concurrently.
Hi, Nice tutorial, but I guess you made a little mistake when it came to read response channel. In AXI we don't have any read response channel, rather we have read data channel which itself transfer the read response with read read data. Cheers!
Hi, Do you know if I can use AXI on virtex 7 ultrascales? The datasheet says it uses a zynq controller but it is a black box. I am a little confused. My design will have several IPs/cores but zynq boards have too little LUs for me. Thank you!
This is really good. You explaining things with examples. But i have a little doubt , there is no such word like read response in arm axi specification manual. I think by read response (17:55) you mean read data, that is transfer from slave to master as response.
sir. How many channels are involved in the read transaction( ie when master reads the data from the slave)..will master sends the address and receives the data from the same channel? I THINK THE FIVE CHANNELS ARE 1.read address channel 2.read data channel 3.write address channel 4.write data channel 5.write response channel are the read data and read response channels same?
Hi. Yes, read data and read response are the same. And the reason is simply, beacause it is a read operation and practically, the answer is the data which is comming back to the master from the slave.
Set speed to 1.5) Nice video
Most useful comment. Thanks.
why u know this ???!!!=))
lmao thanks for the heads up
Perfect speed!
Listening at normal speed sounds so wrong after doing this for a few mins
Thanks for the tutorial, I'm not a native speaker but I can understand and follow your tutorial perfectly. Best Regards!!
dear Mohammad,
many thanks for these well organized tutorial.
I also watched all your video on fpga design.
huge thanks for sharing them.
sweet, thank you so much, I already thought I'd never find good introductory resources on FPGA developement! Hope you find the time to keep up with these tutorials!
A precise and an informative video. Glad to see such Wonderful professor out there helping hobbyist to get the stuff done!
Thank you for the video, you teach from basic ideas is very helpful.
And the speed of your talk is very kind for non native English speaker.
Thank you very much.
Thanks for the tutorial. There isn't much for Zync tutorials out there.
i was proceeding for SoC design and validation training and your videos provided more than a kick start! and your content was quite better than others like everything i wanted. Thanks and love from India
What's your role right now?
Thank you so much for this series! This helps me a lot with my project on a tight timeline... I'm learning a lot!
Abarajithan Gnaneswaran What is your project on?
Nice tutorial. You sound like Darth Vader, though.
You're a genius :-)
Thank you for such a great tutorial with deep explanations. Thanks a million
thank you so much
Thank you for very informative video, kindly upload the video of working of DDR controller
hi Mohammad, very good initiative by you! Well done mate
Thanks for the presentation.
Good introductory tutorial!! Thank you
Thanks Mohammad, valuable video.
Nice video,but what is use of buying an FPGA if follow the protocol to communicate internal modules when practically it's works serially rather than we bought FPGA to develop working things concurrently.
Will you please recommend me videos on AXI 4 Lite. As our Project is based on AXI4 Lite."Design and verification of AXI Lite Protocol"
ممد دمت گرم❤
appreciable job dude
Great start, thank you!
Hi,
Nice tutorial, but I guess you made a little mistake when it came to read response channel.
In AXI we don't have any read response channel, rather we have read data channel which itself transfer the read response with read read data.
Cheers!
thats right
Great tutorial.. Thanks!
Hi, Do you know if I can use AXI on virtex 7 ultrascales? The datasheet says it uses a zynq controller but it is a black box. I am a little confused. My design will have several IPs/cores but zynq boards have too little LUs for me.
Thank you!
Thanks for the tutorial
Thanks a lot, it's very useful to me
My Image processing project when implemented in XILINX ISE is now showing maximum frequency of 161.829 MHZ. It can be implemented on artix -7 or not
NICE VIDEO! THANK YOU
thank you from Viet Nam
I'm from Vietnam too ^^!
This is really good. You explaining things with examples. But i have a little doubt , there is no such word like read response in arm axi specification manual. I think by read response (17:55) you mean read data, that is transfer from slave to master as response.
yup thats true
GREAT VIDEO, THANKS
Hello can anybody please tell me what is the maximum frequency does ARTIX-7 FPGA can operate...
Nice job!
HELLO THANKS FOR YOUR PRESENTATION PLEAS CAN I MAKE CODESIGNE WITH AXI?
press x2 to increase speech speed, goood tuto
I visited ur web page i is really nice
Thank You......
sir.
How many channels are involved in the read transaction( ie when master reads the data from the slave)..will master sends the address and receives the data from the same channel? I THINK THE FIVE CHANNELS ARE
1.read address channel
2.read data channel
3.write address channel
4.write data channel
5.write response channel
are the read data and read response channels same?
Hi. Yes, read data and read response are the same. And the reason is simply, beacause it is a read operation and practically, the answer is the data which is comming back to the master from the slave.
I have some questions regarding AXI DMA, is it possible to have a call to discuss them please?
Thanks a lot
can you explain about xilinx ip Aurora 8b/10b protocol it's working
Hi, is there any chance to get this presentation? :)
Nice video. We are using aurora IP 8b/10b.there are connections with AXI.Can u tell me what those are?
raju CHINNI Hi Raju, look here : ;) www.xilinx.com/support/documentation/ip_documentation/aurora_8b10b/v10_3/pg046-aurora-8b10b.pdf Page 8
WILL YOU SUGGEST PROJECTS ON AXI4 LITE WILL COMPLETE IN 15 DAYS
CiaoDovrei cominciare a sviluppare su Zynq 7020 + Cortex A9, con Xilinx Vivado per FPGA. Come posso contattarti?Marco
+marco gottardo Just watch these videos one after another and try to do the same on your own zed board. you will get where you want. in bocca al lupo!
Nice! Thank you
Set speed to 1.5x or even to 2x
Also, skip the first half of the video where he hasn't even got to talking about AXI!
Sir, How can be the input image taken to AXI interface
image you mean a picture? using axi dma
please do share a link
Good stuff, sound is less fucked on 1.25 speed
@ 19:10, read response channel? I dont believe there is a read response channel
hum! interesting ;) Your own AXI standard :D
A mighty effort indeed.Congratulations.
Nevertheless,I would appreciate it if videos are shorter and also they progress faster.
Thanks
Thanks
it's more convenient to play at 1.25 speed. it sounds more like humans.. wkwk
I think 1.5 much more fluently
You should talk slower and make the lecture 5 hours.
Audio quality is very bad
+Lumina Inova hi yes sorry for that,
this was the first first video i created.
+Lumina Inova I think it's actually kind of funny. He sounds like a robot. I like it.