How to Add External Boards In Xilinx Vivado Design Suite
HTML-код
- Опубликовано: 19 авг 2024
- A quick glance at how to add the external boards i.e. Zedboard, Zybo, etc., in the Xilinx Vivado Design Suite
Steps:
1- Download the board files from diligent's website (digilent.com/r...)
2- Unzip or Extract the folder
3- Goto vivado-boards-master
ew\board_files
4- Copy the required boards' directories from here
5- Goto C:\Xilinx\Vivado\2018.2\data\boards\board_files (Check version and installation path in your case)
6- Paste the copied directories here
7- Launch Xilinx Vivado Design Suite now
8- You should the new board in the 'Boards' tab
9- There you go!
Thanks!
Disclaimer: This video is created for educational purposes and has nothing to do with any hardware or software development companies.
Thanks for this , Helped with my uni assignment!
Glad it helped!
Thank you!!! I did this in Vivado 2020.1. 😄
Great job!
Thanks for the video! easy to follow :)
Glad it was helpful!
I dont have board_file folder in my directory!
You can create one hopefully it should work
i tired this did not work@@GetitQuickly
my vivado 2023 dont have board_files. Can you help me
In vivado, navigate to Tools -> Settings -> Vivado Store -> Board Repository and add your board file path.
I found it!
In Vivado, navigate to [Tools] -> [Settins] -> [Vivado Store] -> [Board Repository]. Then, add the specified path.
Probably you can repeat the process that I explained in the video. Download the board files and copy them to the installation location.
Good to know. Thanks for sharing. :)
Thanks you!! I did this in Vivado2018.3.
But I'm looking for a board part with available IOBs number of about 1500. Can you help me?
I need that for my project! Thanks!!
Not sure what your ask is. Are you looking for an FPGA with 1500 physical IO pins?
@@GetitQuickly yes, I'm looking for that. Sorry, my english skill are not good. Thanks
@@nhatle1719 Not a problem we all are students forever.
Also, when I press cancel,
TCL Console shows this
startgroup
create_bd_cell -type ip -vlnv xilinx.com:ip:mig_7series:4.1 mig_7series_0
apply_board_connection -board_interface "ddr2_sdram" -ip_intf "mig_7series_0/mig_ddr_interface" -diagram "design_1"
INFO: [board_interface 100-100] set_property CONFIG.BOARD_MIG_PARAM ddr2_sdram [get_bd_cells -quiet /mig_7series_0]
INFO: [Common 17-365] Interrupt caught but 'apply_board_connection' cannot be canceled. Please wait for command to finish.
Have you loaded the board successfully with "mig.prj" file inside?
I did it in vivado 2018.2 (I wanted Nexys 4 DDR)
But it keeps loading when i try to place components
TCL Console shows this:
startgroup
create_bd_cell -type ip -vlnv xilinx.com:ip:mig_7series:4.1 mig_7series_0
apply_board_connection -board_interface "ddr2_sdram" -ip_intf "mig_7series_0/mig_ddr_interface" -diagram "design_1"
INFO: [board_interface 100-100] set_property CONFIG.BOARD_MIG_PARAM ddr2_sdram [get_bd_cells -quiet /mig_7series_0]
Please tell me how to fix this....
Make sure you have "mig.prj" in your board files folder for this folder.
@@GetitQuickly yes
It is present
design_1_mig_7series_0_2
1
1
OFF
1024
ON
Enabled
xc7a100t-csg324/-1
2.2
No Buffer
Use System Clock
ACTIVE LOW
FALSE
1
50 Ohms
0
DDR2_SDRAM/Components/MT47H64M16HR-25E
3077
1.8V
4:1
199.995
1
1200
12.000
1
1
1
1
16
1
1
Disabled
Normal
FALSE
13
10
3
134217728
BANK_ROW_COLUMN
8
Sequential
5
Normal
No
Fast exit
5
Enable-Normal
Fullstrength
Enable
1
50ohms
0
OCD Exit
Enable
Disable
Enable
AXI
RD_PRI_REG
27
64
1
0
These are it's contents
My Vivado version is 2018.2
And I am able to place other components,
The issue is only with the DDR2 SDRAM