Getting Started with FPGA Design #2: Creating a Base Vivado Project for Digilent's Arty Z7

[@harry_kr]

Awesome tutorial, very clear, thanks for talking through every step!

[@GlennHope]

This was so helpful and well-presented! Thank you so much. I really struggled with how many tutorials online were out of date or just skipped important steps, and I appreciated the clarity you brought to it. Thank you! (One small unimportant thing, I think the description of this video is incorrect, it looks like it might be the description for another video.)

[@DigilentInc]

Thanks for the keen eyes, Glenn! We got it fixed!

[@totoislearningcodes8790]

I followed all the steps, but when I generated the auto wrapper, Verilog file doesn't contain IOBUFs. I thought I may have missed something, so I tried again, but I got the same result. As my wrapper file doesn't create IOBUF, I can't continue the #5 which requires the connection for LED output... I am not sure if it's the version issue. I am using 2022.2.2 version.

[@GuillermoPerezGuillen]

Thanks a lot ...

[@dineshkumar-kg3ir]

thank you for video :)