VERILOG MODELING EXAMPLES

[@QwertyQwerty-so4kw]

Fantastic lecture. A lot of thx

[@iwbnwif]

@29:13 I think the built-in gates should be in lower case for iverilog to compile.

[@nikhilteja7018]

14:40 Why did we use mux16 to1 M' instead of 'mux16to1 DUT'

[@Gate_IITB]

We can give any name to a module that is called( instantiated), therefore, we can use both DUT or M anything that goes good to you

[@debabrata2137]

14:35 end_purpose of monitor statement

[@mrpossible5696]

7:08

[@sonalikangralkar1996]

sir how to represent complex number in verilog

[@knowledgeunlimited]

There is a concept called CBNS ( complex binary number system) refer that