The best video about verilog for beginners out there!! I' ve seen many of them that are 20-40 minutes long and i couldn't understand a single word. Great work bro!!!
even though it isn't a programming language, it is very similar to object oriented languages class -> module wire -> variable module adder(o,x,y) -> constructor this is very similar to c++. your explanation is amazing!! thanks for putting in so much effort
as a computer science student I was researching about vhdl, after around 10 hours of reading and watching I decided to check how verilog works and found this video. I think I might want to learn verilog instead.
Wow an amazing way to explain such sensitive language for the dumbs like me.. Please give me more links of your video I wanna learn whole RTL from you.
It's like PLC languages when they were more basic than they are now. My favorite since I was trained using S7 with LOGO!, a Click and Drag Logic Gates and Compile, is FBD (Function Block Diagram). How far am I from machine code or is it really not so advanced for stability’s sake? In that regard, my favorite quote is : "If I would deliver code like the folks from windows do, I would lose my job immediately"
Very good introduction, thanks. It somewhat begs the questions "wires?". Why not do it in the proceedural way of simly passing the output of one function (module) into the input of another? Having the wire declared independently looks like it can cause problems.... surely it allows you to have the one wire as the output of more than one module? Why have a language grammar which allows you do that by having a wire exist as a seperate entity to the inputs and outputs? Whilst a wire is exactly that in the real world... independent of the circuits you put it in... in the world of circuit design you don't want wires to be floating around on their own.
This short 5 minute video is the best available on verilog
Dude even after 7 years i would agree to that
Yes
After 10 years still holds true
6 years after, and I agree. I was only made aware of hdl a while ago and I already understand it and verilog. Straightforward video, I love it
Remains undefeated
The best video about verilog for beginners out there!! I' ve seen many of them that are 20-40 minutes long and i couldn't understand a single word. Great work bro!!!
Pretty intuitive, this should be the best Verilog introduction video ever.
This video is the BEST way to understand a whole frickin topic in 5 mins. Literally the best video for beginners
Very well organized! This is the most coherent description I've found. Thanks!
I have been searching for this exact video for three days you are an absolute lifesaver thank you
RESPECT BROTHER !!! 4 min video>>>>prof's 1 hour lecture
Shortest, simplest and best explanation on Verilog!
Best introduction to Verilog!
Previously I was thinking that it is a programming language.
even though it isn't a programming language, it is very similar to object oriented languages
class -> module
wire -> variable
module adder(o,x,y) -> constructor
this is very similar to c++.
your explanation is amazing!! thanks for putting in so much effort
excellent. absolutely excellent! Love the simplicity in the explanartion and the straight fordwardness
You know what RUclips, next time put this video as the first suggestion for Verilog. Not some company videos nobody will easily understand.
The quickest video to understand what the Verilog is. Thx.
awesome 5 minutes of my life searching here and there for verilog basics
One of the best video got so far, clear, crisp..
the best video about Verilog, the vlogger is smart for sure.
This video is the best video about verilog which i understood clearly.
Sir, thank you so much! Your video was not only helpful but gave me an excellent start to my verilog learning experience.
This video will definitely save my test *peace*
Excellent explanation thanx
Simple and Sweet. Thanks for the informative video☺
This video refers to structural hardware description, but hardware description languages also provide rtl description
Sir I am beginner simple study and systematic way cleary explain.thanks lot
best video i found for verilog. More please
This is the best organized video........take love
even after years still the best. bless your soul
Thank you so much it simplifies the core of understanding Verilog with in 5 minutes👏
Excellent video ! I been trying to learn verilog for a while and this really helped me understand it better.
Simple and straight forward! Thank you!
Sir your explanation is best you should must make more videos on verilog as well as system verilog and UVM
The best verilog tutorial I ever seen :)
Wow, now I understand what Verilog actually is, thanx!
This is the best short video for verilog basic
Wow this was super helpful!!! Thank god i got to this before my exams came up
very easier beginning for learner. thankyou sir...
Thanks for solving my doubts about verilog
Best Video Ever U seen About Iverilog
as a computer science student I was researching about vhdl, after around 10 hours of reading and watching I decided to check how verilog works and found this video. I think I might want to learn verilog instead.
Simple and on the point! Best explanation
Very well explained. Thank you. Can you make more ruboost tutorial about Verilog.
Beautiful !!! The world needs more FPGAs
it tok me exactly 5 mins to understand . nice job
Amazingly concise and so beginner-friendly
Best video for beginners.
amazing, love the quick bite info style tysm
😂😂I watched 4 videos on verilog ,and this single video explained content of those 4 videos. Superb explanation.
Great video, I learned more about verilog!
waw...superb teaching technique....thank u
Very concise and clear description!
Thank you for your simple and understandable video.
you're a legend mate
Thanks ! Your explanation was clear !
great start, I wish there was a full course
Excellent video
Exceptionally good intro. Nicely done.
You sir a amazing! I thought they only taught VHDL in the midwest, but I guess I'm wrong.
Excellent bro.. ❤️👑
Amazing Video !
Btw, Really shocked when i knew that Verilog does not describe bedrooms :"D
Oh my God. Thank you. Seriously
such a great explanation, thank you
Really wonderful expanation ..
Thanks! Excellent explanation.
why are you stopped making videos on verilogs, its so nice with great and relateble examples
superb video thank you thank you thank you so so much :D
You just crushed it bro.
Woah man! Thank you so much!!! 😊 Really appreciate your efforts!
amazing video
Best video for verilog
Okay, this was amazing. Thank you
extremely well explained. Thank you sir :)
impressive and informative!
Great short description of Verilog
Been reading websites about Verilog. Why can't websites explain any clearer like your videos. Thanks!
THANK YOU! The visual aids helped alot!
Amazing Video Sir! Kindly make such a video on VHDL
Very well presented ...
Thank you so much . You are awesome!!!
Very good introduction to Verilog !
this is awesome... sir
Wow an amazing way to explain such sensitive language for the dumbs like me.. Please give me more links of your video I wanna learn whole RTL from you.
this 4 min video is better than intel's 50 min video.
It's like PLC languages when they were more basic than they are now.
My favorite since I was trained using S7 with LOGO!, a Click and Drag Logic Gates and Compile, is FBD (Function Block Diagram).
How far am I from machine code or is it really not so advanced for stability’s sake? In that regard, my favorite quote is : "If I would deliver code like the folks from windows do, I would lose my job immediately"
Nice video, do more
excellent...
So nice thanks
Awesome
This is amazing!
Best video ever
Very good introduction, thanks.
It somewhat begs the questions "wires?".
Why not do it in the proceedural way of simly passing the output of one function (module) into the input of another?
Having the wire declared independently looks like it can cause problems.... surely it allows you to have the one wire as the output of more than one module?
Why have a language grammar which allows you do that by having a wire exist as a seperate entity to the inputs and outputs?
Whilst a wire is exactly that in the real world... independent of the circuits you put it in... in the world of circuit design you don't want wires to be floating around on their own.
Thanks, It was very clear.
best one
Awesome!!! Thanks a bunch!!!
that was great !, dont u have a playlist on verilog coding /xilinx ??
very good, thanks
can we use assign statement?
for example
assign or_wire= x|y ;
assign not_wire= ~y ;
assign o=or_wire & not_wire ;
sir plzz make A playlist on complete verilog or plzz suggest a book for verilog
Fantastic, thank you!
plz make more videos..
Fucking excellent bro. Nice
really cool video, thanks :D