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In IF why we use pc+1

in 18:49, explicit association should be "<.> <ports_from_module>(<ports_from_testbench>)", anyone can notice and reply please

15:07 can't we achieve the same functionality using blocking assignment?

3:53 isn't 1^x = x' (x complement)?

6:34 In non blocking condition what will be the result when time delays are different

Thank you for this amazing series Sir❤

9:26 count has to be intialised to zero right??

in time 10:20 state diagram redundant states are there sir

Thankyou sir !!!

where we can download the notes??

I guess for the modified method, in last part you forgot to write next state =S1 and S2 in that 2nd always block

where can i get this ppt

17:00

28:00

in full adder circuit there is no 3 xor circuit present and some verilog code is not correct , please make new playlist

use delay #1 before display, soo that the input and output are settled before display. Now you will get correct Output.

14:40 Why did we use mux16 to1 M' instead of 'mux16to1 DUT'

why is there a latch at the last stage , we can directly transfer the output, is it the necessity of code or necessity of the question??

Always is checking posedge or negedge of clock. But clock generation code is not written. clk1 =~clk1 clk2 = ~clk2

Why need temporary variable for both a and b . A single temporary variable is enough to swap. a = 8 ; b =5; temp = a; a = b; b = temp; output: a = 5 ; b = 8

Here I think we cannot instantiate any modules/UDP inside a UDP. But how did you instantiate TFF UDP inside the ripple_counter UDP at 26:32 ( which is a UDP)??

Very clear, thank you for your service 🫡

Isn't that decoder a dmux ??

It's Verilog or system Verilog

31:50 at examles the parameter up=2'b00 and so on...i think it could be like this.

In the MUX Module, why is the sel not 4 bits?

in palnitkar it is written that multidimensional arrays are not permitted in verilog, integer matrix[7:0][15:0] this is an illelgal declaration in verilog. which one to follow sir's or book?

man this is so hard

At 13:00, third line, S=1 is wrong, it should be S=0.

why do we have built in primitives? while we can already implement things behaviorally like "assign x=a|b;" instead of "or (x,a,b);"? does those primitives serve some different purpose?

at 20.34 , clr =1 is applied after 7 (2+5), not at the edge of clk

*To download pdf notes* *1* Type hardware modelling using verilog indranil sengupta notes . *2* go to assignments (see at bottom) & download it as zip.

But sir how can at 26:48 the t be modelled as a latch as it is defined as a net data type and you said that net data types can only be modelled as wire??

What is the difference between a task and a module?

what is difference between ex-6.(a) and ex-2 ?? Why synthesis tool will do optimization in different way ,basically in such cases, how many Flip-Flop should be generated ??

we want the file source of this piplined please

Best sleeping Medicine ever

very good video, it really help my learning

THANK YOU!!! love this course

This guy is literally the goat. If your seeing this and you want to learn verilog you have to watch this whole series.

This guy has taught me so much, so concise so wise. Thank you professor Sengupta!

1 1 1 & 0 0 0 is not written

In the last Moorey machine code, state has to be initialized to some state: reg [1:0] state=00;

what is the use of stage-4, why cant we perform that memory write in stage-3 itself?

This is why IITs are IITs!

eg:4 of ram3 we do not declare any signal like read, why should we consider that "read_signal" in the ram_test,,why?????

At 15:00 q1=a; #5 q2=q1; Is it possible making like this by introducing time delay at q2 assignment ?

@harir3116 can you please send me the PPT

In the last test bench of adder circuit what is the effect of myseed=15 ? Means what will be the effect of value 15 here?

can anyone explain me the logic of parity