VERILOG MODELING OF THE PROCESSOR (PART 1)

[@douggale5962]

I love cheerful professors like this one. Great job professor!

[@annsgal2025]

I am a software engineer trying to learn about hardware. This lecture series is invaluable.

[@shirsenduacharyya9443]

Thank You Sir, it was a beautiful experience

[@shivanisingh5363]

Thank you so much sir for this wonderful lecture series

[@artbuff2288]

Thank you for this series sir!! Much useful 💯

[@subhashvemula3363]

Thank you so much sir, This lecture series helped a lot while doing my course project

[@architsundriyal1527]

what was your project title?????

[@Golukumar-vj6kk]

Thank you sir ❤

[@xenderlive4865]

The opcodes of last example are wrong, pls check

[@user-rz2ge1wh1s]

can you send the correct ones

[@harshithambati9070]

Sir I am not able to implement this processor in vivado due to not having output pins for this verilog code. So, what should be output ports. Can we declare those PC, IF_ID_IR etc., as output ports for running implementation

[@varunv77]

@harshithambati9070 Hii..even mine im not able to implement the testbench code as it is showing errors at the for loop...im not able to understand how to correct that also....if u have found the correct code can u please send me that code

[@pekka6029]

​@@varunv77bro use k=k+1 instead of k++ in for loop
Also can you help me
I am not getting signals like pc , if_id_ir etc in the simulation window can you help me fixing this

[@pekka6029]

Have you find the solution?
If so please help me also

[@varunv77]

​@@pekka6029 no bro....actually i tried what u told me to change....and there were no errors ...thank u bro....but it did not open the schematic design of that when i implemented the rtl analysis...donno why?
Did u get the ans?

[@pekka6029]

@@varunv77 bro give me ur any contact insta or else i will contact u there