VERILOG MODELING OF THE PROCESSOR (PART 1)

[@user-oe7ln5fb2y]

Why are we assigning every latch after 2s except when the input is 0?

[@kaustuvsawarn4039]

Sir there is an error in the *memory block* in Load statement can you please tell me what it is and how to correct it as well.
Thank you sir ur videos are amazing and helped me a lot.

[@horrorspidey7033]

got the same problem, did you get the solution?

[@kapilsingla1228]

bro there is no error where you have mentioned register bank rewrite its name insted of reg put it regbank then your code will work

[@astrojetmodel]

Dear sir, thank you very much for the video. After the synthesis I have a problem in the EX stage in the line of TAKEN_BRANCH

[@radheshyamshaw8672]

got the same problem, did u get the solution?

[@astrojetmodel]

@@radheshyamshaw8672 I removed this line from the EX stage and placed it before the if in the IF stage. it works perfectly.
TAKEN_BRANCH

[@astrojetmodel]

@@radheshyamshaw8672 If you need it send me an email and I'll send you the correct code.

[@pavan_pelleti]

your mail ID please?
@@astrojetmodel

[@HarshKrSingh]

@@astrojetmodel can i get your email id

[@ANKITMAURYA-sj9dg]

sir in coding you used main memory and instruction memory same but in previous lecture u said to control hazard we take it different?

[@vandan5036]

you can separate it if you want it just defined it in the HEADER