Design Representation

[@jumblebee6018]

Quick access revision
1:22 design representation
2:41 Y (wye) diagram
5:08 more on Y diagram contd.
10:04 Behavioral representation
11:02 Behav. repr. example full_adder
12:28 Behav. repr. example (verilog boolean exprsn.)
14:42 Behav. repr. example (verilog truth table)
18:08 Structural representation
19:51 Struc. repr. example (4b ripple carry adder)
21:13 Struc. repr. example (conceptual repr.)
22:04 Struc. repr. example (verilog 4b RC adder)
27:04 Physical representation
27:49 Phy. repr. example (partial description in verilog)
29:10 Digital IC design (a quick look)
END OF LECTURE

[@arafay142000]

Verilog HDL Complete Series | Lecture 3 - Part 1 | Data Types in Verilog HDL by FPGA made Easy. Subscribe to the channel "FPGA made Easy".

[@user-yr1qd7nr8v]

very good video, it really help my learning

[@meanpillscasper]

Great lesson as always. Thank you.

[@Random.PCB.]

Very clear, thank you for your service 🫡

[@mrpossible5696]

20:01

[@TharunMalla]

where we can download the notes??

[@anirbanpradhan9870]

sir can you tell me from where im supposed to get the slides for these lectures ?
thank you in advance :)

[@lazy.researcher]

register for the course in nptel official website and there u will get the slide

[@saisurya6858]

@@lazy.researcher could you please share a link or google drive, where i can access those. Thanks in advance!

[@arafay142000]

Verilog HDL Complete Series | Lecture 3 - Part 1 | Data Types in Verilog HDL by FPGA made Easy. Subscribe to the channel "FPGA made Easy".

[@VaishnaviN-hf3dq]

heyy did you get slides?pleaase share if you get

[@bidhanroy9295]

1 1 1 & 0 0 0 is not written