VERILOG LANGUAGE FEATURES (PART 1)

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  • Опубликовано: 21 авг 2017

Комментарии • 4

  • @anuragagarwal4576
    @anuragagarwal4576 3 года назад +5

    @29:16 Shouldn't we have to add " wire t1, t2 " also ?

    • @suswakath3819
      @suswakath3819 3 года назад

      Yes, it must be added. It is an error in the slide.

    • @anupammathur17
      @anupammathur17 11 месяцев назад +1

      Yes, that's the mistake in the slide.