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in last module "simple_latch", shouldn't 't' be of type 'reg' as it has been assigned inside 'always'?
in 18:49, explicit association should be " ()", anyone can notice and reply please
But sir how can at 26:48 the t be modelled as a latch as it is defined as a net data type and you said that net data types can only be modelled as wire??
I think there is a mistake there. I think ' t ' should have been declared as a variable of type ' reg ' .
@@guhanrajasekar5993 yes i also feel the same , but it is interesting that no one noticed in 6 yrs!!😲😲
Oo i noticed after reading this ...that should be reg.
@@sakshisingh4197 Can you explain d_out can't be reg? As it is used on the left side ryt? I believe both t and d_out should be declared as reg.
3:53 isn't 1^x = x' (x complement)?
no.. 1 ^ X= X
in last module "simple_latch", shouldn't 't' be of type 'reg' as it has been assigned inside 'always'?
in 18:49, explicit association should be " ()", anyone can notice and reply please
But sir how can at 26:48 the t be modelled as a latch as it is defined as a net data type and you said that net data types can only be modelled as wire??
I think there is a mistake there. I think ' t ' should have been declared as a variable of type ' reg ' .
@@guhanrajasekar5993 yes i also feel the same , but it is interesting that no one noticed in 6 yrs!!😲😲
Oo i noticed after reading this ...that should be reg.
@@sakshisingh4197 Can you explain d_out can't be reg? As it is used on the left side ryt? I believe both t and d_out should be declared as reg.
3:53 isn't 1^x = x' (x complement)?
no..
1 ^ X= X