VERILOG DESCRIPTION STYLES

[@vandan5036]

in NAND LATCH it is active low and s is at top and in its front there is q and in front of R there should be q_bar

[@arghya.7098]

yes, you're right

[@UTube4075]

Best book for Verilog????

[@mrkumar7181]

Why reg is not used ?

[@shirsenduacharyya9443]

the decoder code is showing error and non synthesizable- ERROR - sel is not a constant
module Simple_decoder_1_to_4(in,sel,out);
input in;
input [0:1]sel;
output [0:3] out;
assign out[sel]=in; // when LHS is variable we get a decoder
endmodule

[@arghya.7098]

you used 3 variables but declared 2 variables. that might cause an error

[@nenavathharisingh3231]

Isn't that decoder a dmux ??

[@arghya.7098]

i guess he mistakenly told demux and decoder as same thing

[@arghyaray9011]

Can anyone help on the following !!!
The decoder code is showing error and non synthesizable- ERROR - sel is not a constant
module Simple_decoder_1_to_4(in,sel,out);
input in;
input [0:1]sel;
output [0:3] out;
assign out[sel]=in; // when LHS is variable we get a decoder
endmodule

[@abhishekagrawal542]

but decoder ckt will not having selection line

[@arghya.7098]

you used 3 variables but declared 2 variables. that might cause an error

[@mrpossible5696]

Y