3:18 - 6:11 procedural assignment and its characteristics. 6:16 blocking assignment 17:10 non blocking assignment, 17:24 non blocking assignments are executed concurrently.
Why need temporary variable for both a and b . A single temporary variable is enough to swap. a = 8 ; b =5; temp = a; a = b; b = temp; output: a = 5 ; b = 8
@22:26 Both the assignments are in different always block. So they should not be blocking each other. Swapping should take place. Please clear the doubt?
We don't know which statement will execute first right? (as both of them are set to execute simultaneously), since neither blocks out the other. Thus, there is a race condition.
It boils down to compiler regions (NBA, Pre, Post, active...), all (entire module/verilog_file) the NBA statements are evaluated together (doesn't matter whether we have more than one 'always' or 'initial' blocks). Thus, swapping takes place. Refer about regions in verilog compiler/simulator@@DIVITSHARMA-nj9hn
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3:18 - 6:11 procedural assignment and its characteristics.
6:16 blocking assignment
17:10 non blocking assignment, 17:24 non blocking assignments are executed concurrently.
Why need temporary variable for both a and b . A single temporary variable is enough to swap.
a = 8 ; b =5;
temp = a;
a = b;
b = temp;
output: a = 5 ; b = 8
this is also fine.you can do it with single variable also
@@sakshisingh4197 how?? Is that what you mean by using non blocking assignments?
@22:26 Both the assignments are in different always block. So they should not be blocking each other. Swapping should take place. Please clear the doubt?
Yes I too got the same doubt.
We don't know which statement will execute first right? (as both of them are set to execute simultaneously), since neither blocks out the other. Thus, there is a race condition.
but for non-blocking example , they are in different block , so their non-blocking effect will not apply na ?
It boils down to compiler regions (NBA, Pre, Post, active...), all (entire module/verilog_file) the NBA statements are evaluated together (doesn't matter whether we have more than one 'always' or 'initial' blocks). Thus, swapping takes place.
Refer about regions in verilog compiler/simulator@@DIVITSHARMA-nj9hn
i covered ur previous oll lectures.
Thanks for uploading latest version on very log concepts thanks to NPTEL
@ 12:46 the variable A and B are 32 bit size so instead of 31'b0 assigning, i think 32'b0 will come?? Please check.
Tnk u sir.... I need reference book for verilog kindly can u suggest me sir
Samir palnitkar is a good book for verilog.
Viabhav tarate is also good for basic verilog programming @@knowledgeunlimited
thank you
Ty
@2:56
17:03