PIPELINE MODELING (PART 2)

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  • Опубликовано: 20 сен 2017

Комментарии • 5

  • @pavan_pelleti
    @pavan_pelleti 9 месяцев назад

    what is the use of stage-4, why cant we perform that memory write in stage-3 itself?

  • @dhaneshprabhu72
    @dhaneshprabhu72 3 года назад

    Why are connecting addr to every latch and not bypassing it to the last latch

  • @javivi2097
    @javivi2097 Год назад +2

    The case statement of stage 2 don't should be to use L12_func instead of func?

  • @alkakumari2774
    @alkakumari2774 4 года назад +2

    Why we are taking negative edge for clk2