FOPLP 面板級扇出型封裝 Fan-Out Panel-Level Packaging, FOPLP

＃foplp #面板級封裝 #台積電 ＃先進封裝
先進製程節點微縮伴隨製造工藝難度提高，每逢跨入新的節點的初期成本以非線性方式成長，如何有效壓低成本成為晶圓代工業者的重要課題。晶圓切成方形晶片造成的邊角料損失為目前半導體業者試圖解決以降低成本的其中一種方案，面板級的概念在今年台積電法說提出後引起市場廣大迴響，以方形基板堆疊晶片不僅可減少不必要的耗損，更可以提升生產效率，基板的尺寸可以比晶圓大上數倍。
The advancement of semiconductor manufacturing processes has led to increased complexity and costs, particularly as companies transition to smaller process nodes. This non-linear growth in initial costs at each new node has made cost reduction a critical issue for wafer foundries. One proposed solution to mitigate costs is the shift from traditional circular wafers to square substrates, which can significantly reduce edge waste during chip cutting. This concept gained traction following TSMC's recent announcements, highlighting that using square substrates not only minimizes unnecessary losses but also enhances production efficiency, as these substrates can be several times larger than standard wafers.
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