"Dual" because the contact-Pins are on both sides of the DIMMS, not because there are chips on both sides. That means "Single- und Double-Sided-DIMMs". But thanks for the other Information.
Just to clarify a little bit more, it is because of the * independent * pins in both sides. SIMMs (Single Inline Memory Modules) have pins at both sides as well but they are redundant.
Dude, its called DIMM because the Pins or Connectors are present in both sides of the module not because the chips are present on two sides. Chips present in both sides is the concept called RANK. Dual Rank - Chips present on both sides of the module, Single Rank - Chips present only on 1 side of the module
Great video! :) I have been reading through the JEDEC DDR3 spec and this video provided a nice visual of what is happening. I am still new to DDR. Quick question @7:15. In a Read operation, once a row address is presented followed by a column address, are we only selecting one single bit that is then presented onto the Data Bus? Since there are 16x cells in parallel per bank, we are accessing 16 individual bits in parallel at the same time? Thanks!
Hey Vince, i think it depends on the burst length x4, x8 which means data will be read or write in burst for example if DDR is x4 then at a time 4bits will be read and 4 will be written. Similar is for x8.
x16 meaning one bank contains 16*16 address which equals 256 addresses per bank, it takes 4 bits to address the row and another 4 bits to address the column, that's 8 bits required to identify a specific 1 bit location out of 256 addresses. watch this to learn more: ruclips.net/video/fpnE6UAfbtU/видео.html
@@obada. are you sure? I think 16x means one bank outputs 16 bits at a time(maybe in bursts according to x4, x8 as Crack Govt Jobs says?). One {row, column} address pair address 16 bits I think.
@@flyxtop I think I was mistakenly referring to a planar row and column only bank. The guy in the video said each chip will output 16 bits at once, that 16 bits chip is divided into 4 banks with each bank having a row, column, and width. Row and column indicate the physical location using 4 binary bits for each, and width indicates the burst length that is how much data of that address to output, in this case it's either 4, 8, or 16 bits per burst and bank, which translates to either 16, 32, or 64 bits per chip.
THANKYOU!!! This explanation including matching pictures was nowhere else on the internet, but you had it on youtube.
Thanks I had so much trouble reading about this without a visual! It seems a lot of people came here for the same reason lol
"Dual" because the contact-Pins are on both sides of the DIMMS, not because there are chips on both sides. That means "Single- und Double-Sided-DIMMs". But thanks for the other Information.
Just to clarify a little bit more, it is because of the * independent * pins in both sides. SIMMs (Single Inline Memory Modules) have pins at both sides as well but they are redundant.
excellent
can you make a video on LPDDR5 how it works , init,trainings,caliberations..etc..
i almost died at 0:49
😂😂
Dude, its called DIMM because the Pins or Connectors are present in both sides of the module not because the chips are present on two sides.
Chips present in both sides is the concept called RANK. Dual Rank - Chips present on both sides of the module, Single Rank - Chips present only on 1 side of the module
Very very useful very very thanks 🙏🙏👍👍
Thank you Sir it helps a lot
Thanks Paritosh Keep watching the videos
Clear one thanks!!!
Thank you so much, I have subbed and liked the video.
Very helpful video
Thanks Anjali
Can I replace my 1rx8 ram with 2rx8 ram in my laptop ..
I think that you are confusing DRAM Array and DRAM Bank. They are different.
Great video! :) I have been reading through the JEDEC DDR3 spec and this video provided a nice visual of what is happening. I am still new to DDR.
Quick question @7:15. In a Read operation, once a row address is presented followed by a column address, are we only selecting one single bit that is then presented onto the Data Bus? Since there are 16x cells in parallel per bank, we are accessing 16 individual bits in parallel at the same time?
Thanks!
Hey Vince, i think it depends on the burst length x4, x8 which means data will be read or write in burst for example if DDR is x4 then at a time 4bits will be read and 4 will be written. Similar is for x8.
x16 meaning one bank contains 16*16 address which equals 256 addresses per bank, it takes 4 bits to address the row and another 4 bits to address the column, that's 8 bits required to identify a specific 1 bit location out of 256 addresses. watch this to learn more:
ruclips.net/video/fpnE6UAfbtU/видео.html
@@obada. are you sure? I think 16x means one bank outputs 16 bits at a time(maybe in bursts according to x4, x8 as Crack Govt Jobs says?). One {row, column} address pair address 16 bits I think.
@@flyxtop
I think I was mistakenly referring to a planar row and column only bank.
The guy in the video said each chip will output 16 bits at once, that 16 bits chip is divided into 4 banks with each bank having a row, column, and width.
Row and column indicate the physical location using 4 binary bits for each, and width indicates the burst length that is how much data of that address to output, in this case it's either 4, 8, or 16 bits per burst and bank, which translates to either 16, 32, or 64 bits per chip.
@@obada. I see. that's good my understanding was correct more or so.
The explanation of DIMM and SIMM is not right. The difference of DIMM and SIMM is 64bit VS. 32bit datawidth.
Thats not how dimm is defined
I think what you are teaching in this video is not 100% correct, DRAM and bank are not the same.
Absolutely Abdul, DRAM is divided into Banks but for just brief purpose I said