Fixed-Bias Configuration of JFET (Mathematical Approach)
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- Опубликовано: 27 дек 2016
- Analog Electronics: Fixed-Bias Configuration of JFET (Mathematical Approach)
Topics Discussed:
1. Fixed-bias configuration of JFET.
2. DC analysis to find out operating point.
3. Approximations in dc analysis.
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i really appreciate your work about it and this video is so so so much helpful to me. i didn't understand JFET biasing while lecture but after watching this video i knew the whole terminology of JFET biasing...so once again thank you so much and keep it up👍
Excellent lecture sir, thank you..!
Excellent lecture !
thanks, sir..this one was easiest from my faculty
thanq soo much for the videos, i really appreciate your work
Thank you so much sir for clearing my this topic
Thank you sir u explanation is super 👏👏
Shouldn't the equation be I(d)=I(dss) *(1-Vgs/Vth)^2
Why is it vgs in point Q?it Should be vds just like in bjt
Thank you, this was very helpful.
your vedios are very very helpfull to me...I m studying in electronics 2 ND year and I didn't understood the basic concepts of analog elec but now after I hav watched your vedios related to my course I hav the basic knowledge and concepts are very clear.. I will recommend ur page to evry one I knw who has problem in understanding....
I appreciate ur approach towards this thanku for making this vedios.. plz keep it up it'll help youth very much...
very effective
Q point coordinate is(as far as i know)---(Vdsq,Idq)
nice video keep it up
thnxx a lot sir
Don't you have the polarity at the gate and source labeled backwards?
Excellent video.
how can we decide the operating point hre ?
becoz in bjt we took q point for both input and output loop ?how wecan decide q point ??
sir I am confused with q point as some books write it as(VDS,ID) what it is really?
Sir when will you upload the OP-AMP lucture...............plz reply
Sir why is vgs kept positive potential in jfet u drew? Doesn't it operate in only 0v or negative vgs
Where positive? In his diagram, Voltage is given negative there, not positive
What is input impedence and output impedence and voltage gain of fixed bias I want that Pls send the link
Is input signal at gate source increase positively or negatively IAM confusing with these signs , suggest me
how the signs are inserted before applying KVL....?????????
All was so good but sir try to explain lectures in urdu or hindi...plz
what will I do I'm mathematical computition if it is p channel?
How to decide signs at gate and drain
Sir i don't understand from where the the circuit came from and why f = 0 hz.
Plz reply
Sir I have one doubt about short circuiting the rg, v=ir(ohm law) so that r =infinity
it is already infinity but the it is the resistance from the Rgs not the resistance you are talking about
What is Shockley equation,sir plz explain it
Id=Idss(1- Vgs/Vp)^2 is known as shockley eqn
Q point is Vdsq
Same doubt
Sir what is the q point of this biading
Then what for u have introduced capacitors sir .What is the use of that....
This is the DC bias to setup operating point of the transistor. The capacitors would couple and decouple the AC component which is to be amplified or impedance matched. (from the best of my knowledge.)
why we are applying negative voltage to gate....sir can u tell me
To make it reverse bias so that we can have the control on Id
Are VD and vds the same
Isn't the Id formula having square?
Why IdRd is taken as negative sir
Sir, when would you done with logic families?
Sir i n some books I'd and Vds are operating point
Is it real
I love when he says "we already know"