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Self-Bias Configuration of JFET (Mathematical Approach)
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- Опубликовано: 2 янв 2017
- Analog Electronics: Self-Bias Configuration of JFET (Mathematical Approach)
Topics Discussed:
1. Comparison between fixed-bias and self-bias configurations.
2. Self-bias configuration of n-channel JFET.
3. Operating point in self-bias configuration.
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Music:
Axol x Alex Skrindo - You [NCS Release]
• Axol x Alex Skrindo - ...
sir you are a genius and thank you so much for your lectures. I thought electronics was hard but i was wrong.
Thank u sir for these lectures.... I like ur way of teaching
Thank you again for these great lectures on transistors
great explanation my dear
You are the best
That input voltage apply positively or negatively?
Thank youuu so much
How did you learn this all things? You are good within every subject
thanks man
Thanks a lot for mathematical approch,,i was trying to do it but couldnt...thanks
great explanation
thanks!
Without using graphical approach. How vould ypu find which root's correct Id value? Because we have two roots.
I have the same question.
is there no graphical approach for fixed bias circuit
Id can be found by applying KVL across drain and source.
plz give us some video of opamps too
tq sir
how do you decided which Id to use as there will be 2 values for Id
Yeah I want to know also
+1
Make a video on op amp sir
How did Vp move up to the numerator from the denominator of the fraction? I don't get it.
He got (1-(Vgs/Vp)) to a common denominator. Vp/Vp = 1. So ((Vp/Vp) - (Vgs/Vp)) can combine to make (Vp-Vgs)/Vp. Where Vgs = IdRs.
Slope decreases and Q pt moves from y-axis ...am I right?! (P.S.new learner)
sir plz reply
how do we know which Id value to use
I think, your exam has gone well ,
So the answer to your question is you will further check the 2 answers and the given Idss , that the correct answer should be less than idss .
Why do ID and IDQ have different balues on other solved problems online??? And how the hell do I get IDQ???
Can these subtitles be removed
Calculate the bias currents for the circuit as shown in Fig. 2 and verify that the transistor Q1 operates in
the forward active region. Assume β=100 and IS=5x10-17A. How much does the collector current,
change if R2 is 1% higher than its nominal value?
🙏🙏🙏🙏🙏🙏 plz sir upload video on op -amp
what is the difference between Id and Idq ? thanks
no difference.... q is added to show that it's an element required to find Q point
Sir will u complete syllabus before gate 2017 i.e opamps etc plz reply
what if vp is not given? and Vgs(off) is given.
Talha Ev vgs (off) = vp
Vgsoff =-vp
Sir Please upload FET small signal model. FET amplifier also
ya please upload jft common sorce ampilier voltage gain dirivation and equlent circuts
🙏
My head hurts.
10:31 its minus 1, why change to minus Vp?
By taking lcm in denominator
Little bit complicated
I'm so fucked tomorrow.
i hope u could write G ans S properly. your G look like s
Sir ye to totally wrong h agr koi thank you bolta h to uska reply de dete ho pr koi question puche to uska koi reply nhi
M ye janna chata hu ki operating point to (Vds,Id) honge na ki (Vgs,Id)
He never give any reply to any one I only seen an ❤ symbol to some cmnt