JFET: Self Bias Configuration Explained (with Solved Examples)
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- Опубликовано: 15 фев 2019
- In this video, the Self Bias configuration for the JFET has been explained. And a few relevant examples have been solved for the Self Bias Configuration.
By watching this video, you will learn the following topics:
0:27 Advantages of Self Bias Configuration over Fixed Bias Configuration
3:04 DC analysis of Self Bias Configuration
7:42 Example 1
12:03 Example 2
17:37 Example 3 (For practice)
The Self Bias Configuration:
The Self Bias configuration is another biasing technique which is mostly used for biasing the JFET.
In this configuration, there is no need to supply the additional voltage to the gate terminal to provide the Gate to Source voltage (Vgs ) to JFET.
The voltage drop across the source resistor provides the required control voltage (Vgs) for the JFET.
Unlike the Fixed Bias configuration, the Self-bias configuration stabilizes the variation in the operating point of the JFET by itself ( which may occur due to the external parameters like temperature)
In this video, the DC analysis of the Self Bias Configuration has been explained and the few relevant examples have been solved.
The other videos related to Field Effect Transistor (FET):
1. What is Field Effect Transistor (FET)?
• What is Field Effect T...
2. Construction and Working JFET
• JFET: Construction and...
3. Transfer Characteristics of JFET
• JFET Transfer Characte...
This video will be helpful to all the students of science and engineering in understanding the Self Bias configuration for the JFET.
#SelfBiasConfiguration
#JFETBiasing
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The timestamps for the different topics covered in the video:
0:27 Advantages of Self Bias Configuration over Fixed Bias Configuration
3:04 DC analysis of Self Bias Configuration
7:42 Example 1
12:03 Example 2
17:37 Example 3 (For practice)
your explanations are almost equivalent to class ones. i wonder how they have so less views considering your are one of the most genuine channel that I've discovered especially useful for the ones who missed their class lectures or want to clear up his/her basics. Anyways, really very helpful videos sir. Mera semester ap k wageh se hi clear ho paega so thanks a ton !!!!!!!!!!!!!!!!!!!
Best online channel for electrical engineering . Keep it up
Answer of Example 3:
Vgs=2.112V
Id=4.2mA
Vds=-4.5V
It is in the saturation region.
Great video simple and straight to the point!
Nice voice and teaching capacity.we should support these videos
What a dedicated teacher you are sir.... Great teacher..
Kudos. Thanks for making these videos.
thanks..it's very useful
Very nicely explained 👍
In example 2, the validation for the p-channel Jfet operated in saturation should be |Vds|>= (Vp-Vgs) right??
For example 3 I got :
Vgs = 2.106v
Id= 4.212mA
Vds= -4.45v
And it is in saturation region
Are these values correct?
And thanks a million for your great explanation.
yes buddy correct
Isn't Vds = -4.47V?
@@kimverlycasem3398 you are right .Vds must be - 4.47 but as you know very small differences
Great video sir 👍👌💚
V_gs = 2.106 V, I_d = 4.212 mA, V_ds = -4.47 V . This also works in the saturated/active region because | V_ds | >= V_p - V_gs is satisfied.
What we should do, if the jfat is not working in saturation?
Better than my prof fr fr
sir please complete the biasing syllabus. and also mosfet moscap cmos lessons
what is the answer for example 3?
How that Vds greater than or equal to Vgs - Vp comes???
Sir, we want a video also on voltage divider bias configuration of JFET.
will try to provide it soon.
How to solve VGS without ID?? I need helppp pls
what about ac analysis ?
I can't solve the quadratic equation part. Any help?
Apply Sridhacharya's formula
Why is vgs is ID not IDxRS? In solved question
Sir, can you make a tutorial on Phase Locked loop?
Soon, I will make a video on it.
how is JFET used as a linear amplifier, where will the AC input be connected ?
Will you be posting example 3 practice solution, thank you.
I= 4.21mA
Vgs= 2.10
Vds=-4.4
i am confused in the polarity of gate terminal in the case of example 3 and example 2 in both cases polarity of gate is positive why it is so as the polarity in example 2 should be of negative as gate terminalfor n type j fet should be negative for reverse biasing if anyone can explain please tell me i ll be thankful to him / her
In the example 2 and 3, there is a p-type JFET. For p-type JFET, Vgs is positive. I hope, it will clear your doubt.
Subtitles are blocking the diagram.
Im confused for the id formula for self biasing. If Vgs= Id×Rs. Original formula for Id is Id = Idss ( 1 - Vgs/Rs)^2. Then why in the formula after substitution, Id = Idss(1-Id/Rs)^2?
Yep bro is skipping tons of steps or maybe he is just yappin nonsense
Sir, subtitles are blocking the circuit.
Vgs = -- Id x Rs not Vgs = Id x Rs, Vgs is positive with respect to ground, Id x Rs is negative with respect to ground.
Ans of the last question:
ID= 4.212mA , VGS=2.106V, VDS= -4.47V, And this JFET is in the saturation region.
why I got Id for first example 6mA?
me too..where did he get the 16.5 Id...I think it should be 12Id
@@mayaisa6087 😆😆😆
I'd = 4.2mA, Vgs = 2.1V, Vds = 4.5V
How did you come up with 16.5 IB?
he multiplied the both side of equation with 36/8 and then rebuild the eq again
While solving why don't u consider units of Id and Vgs I mean one is in mA ani other was Kv
Yes, but the multiplication of mA with kΩ will be in V.
13:53 its IdRs sir, u missed Rs
Can someone tell me how did he got the 16.5 Id in the quadratic equation ex.1...I think it should be 12Id...
At 9:18, just multiply L.H.S and R.H.S by 36/8. And further, by moving (36/8) Id on the other side, you will get it 16.5 Id.
@@ALLABOUTELECTRONICS but the value of Idss is 8mA not 8A
@@agnesasopaj Yes, that is why the final answer Id1 and Id2 are also in mA.
Where is vedio for voltage divider biasing of JFET?
I am unable to find it
It's not covered yet. But it will be covered in the coming months. ( The remaining topics of FET)
Thanks a lot!!😀
How do you simplify the quadratic equation i dont understand
Good Question. I have the same.
Hi, I think many of you finding it difficult. Sol, let me explain it here. Here, Id and Idss are in mA.
Rs is in kilo-ohm.
Now, the equation is Id = Idss ( 1 - Vgs/Vp)^2.
Here. Vgs = - Id x Rs And Vp = -6V
And Idss = 8 mA.
So, it can be written as Id (in mA) = 8 mA x [ 1 - ( - Id ( in mA) x (1 kilo -ohm)/ (-6V))^2
Now, mA and kilo-ohm is V. And in the denominator there is volt. So, overall term will be unitless.
So, overall it can be written as Id ( in mA) = 8 x ( 1 - Id /6)^2
I hope it will clear your doubt.
@@ALLABOUTELECTRONICS Thanks that makes sense.
How did you get Id^2 -16.5+36 from 8/36(36-12Id+36Id^2)?
@@curlyterise8469 i have same qouestion here :/
9:32
Sir, how did you get 16.5 Id in the first example? Can someone enlighten me?
At 9:18, just multiply L.H.S and R.H.S by 36/8. And further, by moving (36/8) Id on the other side, you will get it 16.5 Id.
@@ALLABOUTELECTRONICS Thank you! Now I understand :)
@@ALLABOUTELECTRONICS How?
@@kazuto2151 how?
sir around 9:00 Vgs = -ID x Rs but in the equation u only provide ID for Vgs where does Rs go?
Vgs (V) = - ID(A) x Rs( Ohm)
Rs =1k (Ohm )
Vgs (V) = - ID(mA) *10^-3 * Rs (Ohm)= - ID(mA )* 10^-3*1*10^3= -ID(mA)*1(Ohm) =-ID
Because prof uses mA for ID.
at around 9:07 Ugs shouldnt be -Id*Rs?
Rs [Kohm] also is needed for Idss [mA]
Rs is 1 kilo-ohm. So, it is already taken into account during the calculation.
@@ALLABOUTELECTRONICS Please show us how it was done. Maybe you could explain in the community section. Thanks.
Hi, I think many of you finding it difficult. Sol, let me explain it here. Here, Id and Idss are in mA.
Rs is in kilo-ohm.
Now, the equation is Id = Idss ( 1 - Vgs/Vp)^2.
Here. Vgs = - Id x Rs And Vp = -6V
And Idss = 8 mA.
So, it can be written as Id (in mA) = 8 mA x [ 1 - ( - Id ( in mA) x (1 kilo -ohm)/ (-6V))^2
Now, mA and kilo-ohm is V. And in the denominator there is volt. So, overall term will be unitless.
So, overall it can be written as Id ( in mA) = 8 x ( 1 - Id /6)^2
I hope it will clear your doubt.
@@ALLABOUTELECTRONICS you are stupid for leaving this out of this video.
@@ALLABOUTELECTRONICS i got it thanks a lot!
9:01 , VP is -6 V, why become 6 V ?
Vgs is also negative. Since both Vgs and Vp are negative, the eventual sign in the equation after putting the values remains negative. I hope, it will clear your doubt.
9.18 is quadratic equations'
subtitution correct?
anyway final answer is correct if drain currents
9:06 You state that Vgs = -IdRs yet you only substitute Id in for Vgs. Where does the R go?
R=1kohm so he didn't mention it.
Time 9.04 ma vp =-6 tha tuna +6 kyu liya , aur.fir.13.55 pa vp=+6 tha tuna +6 liya
Matlab dono jagah +6 kyu kaisa???
At 9:02, Vgs = -Id *Rs (Where Rs is 1 kΩ). And Vp is also - 6V, so the minus sign in the numerator and denominator was canceled. That's why +6 is written. I hope it will clear your doubt.
Your work is sketchy...how do you get the quadratic expression ? Don't assume everybody in here knows ..plz do explain how
Hi anvil
I apologize for what I am about to say but you skip over some fricken important steps. Thanks for wasting my time.
Like maybe I in the wrong but why do u say Vgs = -Id*Rs and then you just out Id in to subistute for Vgs..... I dont understand.
@firstname lastname thats not the point.
Cuz Rs = 1 k ohm
how did he get up to ID1=13.91?
I can't solve the quadratic equation part. Any help?