APB Protocol Design and Verification | APB Memory Design | Part 2

Поделиться
HTML-код
  • Опубликовано: 21 июл 2024
  • AMBA APB Protocol design, Advanced Peripheral Bus Protocol is a part of AMBA Family, Used to Connect low performance, low bandwidth peripherals in VLSI SOC. APB Memory is Designed and Read Transfer, APB Write Transfer, APB State diagram is explained in detail with waveforms.
    part 1 APB Protocol Theory: • APB Protocol Read Writ...
    part 2 : APB Protocol Design
    contents:
    0:00 Intro
    0:10 APB Part 1
    0:34 APB Signals
    2:45 Master & Slave
    3:10 Design code Starts
    Follow @exploreelectronics for Basics
    Digital Electronics : • Digital Electronics
    Verilog HDL Basics : • Verilog HDL
    CMOS VLSI Design : • VLSI Design
    Whatsapp Channel : whatsapp.com/channel/0029Va4w...
    Telegram : t.me/VLSI_Jobs_Training

Комментарии • 7

  • @mohanavinashsabbineni626
    @mohanavinashsabbineni626 10 дней назад +3

    Very easy explanation sir
    waiting for testbench part

  • @statusandmore319
    @statusandmore319 18 дней назад +2

    please post part 3 sir

  • @channameshsangannavar4523
    @channameshsangannavar4523 23 дня назад +1

    Good explanation ❤

  • @yaary6663
    @yaary6663 24 дня назад +1

    Very nice sir thank you 🙏

  • @chandankumar-rz6fm
    @chandankumar-rz6fm 14 дней назад +1

    super explanation of code and in part 1 video also superb as i am working on this project to make APB slave i have taken so many intakes from this and i am waiting for the testbench part....please upload it soon........

  • @yaary6663
    @yaary6663 24 дня назад +1

    Please explain on coverage, Assertions, Constraints sir🙏

  • @ExploreElectronicsPlus
    @ExploreElectronicsPlus  27 дней назад +3

    APB Part 1 : ruclips.net/video/zA88cXfbvOg/видео.html
    Follow on Telegram: t.me/VLSI_Jobs_Training