APB Protocol Basics | APB Protocol Explained | APB Interface | APB Bus Protocol | AMBA APB Topology

[@Electronicspedia]

Please Like, Share and Subscribe to my channel ruclips.net/channel/UC3mTACG8vPWsHQFMfxzeDZg

[@keepcalm8420]

Your whole series on APB is really good and probably one of the best made on youtube. Really appreciate your effort. Thank you for the clear explanation. Hope you can make more videos on protocols such as AHB, AXI etc.

[@Electronicspedia]

Hi, thank you so much that you liked my videos, I will definitely come up with more videos on protocols like AHB, AXI and PCIe as well, keep watching Happy learning !!!

[@user-wi1ke7ws5s]

You are very good honestly, in all my years in university i never had a teacher that explains better than you.

[@yogishmurthy9320]

You're explaining in a awesome way sir.
Keeping continuing sir

[@Electronicspedia]

Thank you 😊

[@tarekamrani7155]

Best Teacher Thank you very mutch

[@Electronicspedia]

Thank you 😊

[@sailajapeddakotla8248]

Hope you can make more videos on Protocols

[@kartiknit1]

Very nicely done video! thank you for this. Do you have a video on AXI? If not, please do share it :)

[@rambabukasetty8975]

Nice explanation. Can you upload video on AHB.

[@oviya.n1317]

@10:18 u are saying APB is a single bit transaction. As per the protocol the bus width can be upto 32bit wide. Can u clarify this. ALso at the beginning of the video u are calling APB as single channel. It has got channel for read ,write right?

[@Electronicspedia]

Hi,
It's not single bit, I had said single beat.
Here beat refers to one single transaction in a burst.

[@noufalnishath1937]

very good explanation

[@venkateshprathipati3907]

Thank you so much.

[@venkataravindrabiyyala1759]

sir please do videos for AHB and AXI protocols

[@Electronicspedia]

Sure.

[@anilkumarkurra1314]

Hai sir, shall we logic data type in verilog.
For both input and output?.

[@Electronicspedia]

Yes,
Input logic siga,
Output logic sigb
Both are valid.

[@anilkumarkurra1314]

Okk sir tanq

[@ARUNKUMAR-oy1gk]

@@Electronicspedia but...sir...logic keyword is only for sv right....not in verilog

[@Electronicspedia]

@@ARUNKUMAR-oy1gk yes you are right. Thanks for pointing out.
Actually I have been using system verilog for quite sometime and I often forget what is there verilog and system verilog.

[@ffushiguro]

In verilog
for design
input - wire
Output - reg
For testbench
Input- reg
Output - wire

[@user-oo8vi5cf1x]

Thank you ❤

[@gokulp6878]

Amazing .can you please explain ahb protocol

[@Electronicspedia]

Sure will plan for it. 👍

[@maksymkloka7819]

Keep making videos.

[@shanyuth836]

Very good explanation. could you please explain about axi?

[@reubengeorgemathai7329]

Great video!

[@sankasuvarna1900]

very nice tutorial sir do u take any online training sessions if yes pls share details i will join

[@Electronicspedia]

Hi, No I just make videos here for everyone's benefit. No other online classes.

[@sailajanarayanam7707]

Sir can you explain ahblite topology

[@Electronicspedia]

Sure.

[@navyamalla7362]

nice explanation

[@Muskaanhayat]

Thanks sir

[@neelimareddy4139]

How many slaves are there for an apb