APB Protocol Basics Write | APB Write Transaction | APB Write Transfer | APB waveform | APB Protocol

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  • Опубликовано: 21 июл 2024
  • Hello Guys,
    In this Video, I have explained about APB Protocol Write transfer with waveform. I have covered both APB write without wait cycle and APB write with wait cycle. It takes minimum two (2) clock cycles for one APB transaction.
    Keywords:
    Advanced Peripheral Bus, APB protocol basics, APB interface basics, APB explained, Basics of APB, APB Write Transfer, APB Read Transfer, APB Write Cycle, APB Read Cycle, AMBA Bus Architecture, AMBA Family Protocol, APB Protocol Concepts Overview, APB Overview, APB Tutorial, NPTEL, nptelhrd, AMBA, APB Master, APB Slave, APB Bridge, APB Address Decoding, APB Bus architecture, APB Topology, VLSI, VLSI Design, VLSI Interview Questions, VLSI Design, APB Interview Questions, APB Transfer Slave Error, APB Write transfer with Wait Cycle, APB Read transfer with Wait Cycle, APB Write transfer without Wait Cycle, APB Read transfer without Wait Cycle, APB Setup Phase, APB Access Phase, APB Write transaction, APB Write transaction with wait cycle, APB Write transaction without wait cycle,
    APB Basics and Bus Topology Video : • APB Protocol Basics | ...
    APB Read Transaction : • APB Protocol Basics Re...
    Chapters :
    00:00 - Introduction
    00:35 - APB Write transaction Waveform
    06:11 - APB Write transaction without wait cycle
    10:20 - APB Write transaction with wait cycle
    #APBProtocol #VLSI #APB
    Credits:
    1. A Magical Journey Through Space by Leonell Cassio | / leonellcassio
    Music promoted by www.free-stock-music.com
    Creative Commons Attribution-ShareAlike 3.0 Unported
    creativecommons.org/licenses/...

Комментарии • 13

  • @Electronicspedia
    @Electronicspedia  2 года назад

    Please Like, Share and Subscribe to my channel ruclips.net/channel/UC3mTACG8vPWsHQFMfxzeDZg

  • @user-lq9dh7dp6p
    @user-lq9dh7dp6p 2 месяца назад

    Thank you

  • @arlaharitha1202
    @arlaharitha1202 Год назад +3

    good explanation

  • @reddychowrasta6003
    @reddychowrasta6003 Год назад +1

    The min clock cycle to finish the data transfer is 2 clock xylces so how the transaction terminates within 1cloxk cycles

  • @surajitdas2505
    @surajitdas2505 Год назад

    nicely explained..

  • @electromgaming7242
    @electromgaming7242 2 года назад +4

    sir please,make video tutorials forAHB, AXI and PCIE, Ethernet protocol . As on youtube, no such contant is available , Please help to students, are working in semiconductor industries.

    • @Electronicspedia
      @Electronicspedia  2 года назад +1

      Sure, these i have planned in series. Will cover them. Thanks for suggestions. 👍

  • @neelkamal3385
    @neelkamal3385 2 года назад +2

    Well Explained

  • @vigneshrshankar668
    @vigneshrshankar668 Год назад +3

    Good walk through! Can you do a video on AXI protocol?

  • @user-ks7dv6nd2b
    @user-ks7dv6nd2b 11 месяцев назад

    Sir, why is Penable asserted after one cycle and not asserted with Psel, what is happening between Psel assertion and Penable assertion?