Introduction to Axi Architecture || Amba Axi Bus protocol

[@brucesdx1151]

In the first step, should the sender wait for the ready signal? If it does, wouldn't there be a deadlock? The sender waits for the receiver's ready to raise valid, and the receiver waits for the vaid to raise ready? I think to prevent deadlock, valid and ready cannot depend on each other. If the sender raises valid but receiver is not ready, the sender should simply hold the data and wait.

[@Allaboutvlsii]

Yes ur correct

[@maharshitrivedi9545]

1:36 write response slave-> master

[@poojarianilkumar5125]

Sir , initialy you saying read address channel send the address from slave to master but in the diagram read address channel the address send from master to slave .
Which one is correct?

[@Allaboutvlsii]

Hi so wheather it may be read or write the address will be send from the master only

[@praveenmukkiri6374]

@@Allaboutvlsii Hi Sir, I respect your work, but please make sure if the above statement is correct

[@pinnintieswaraprasad2452]

In read address channel send the address from master to slave this is correct only

[@maharshitrivedi9545]

adress channel always master to slave

[@krutikakhakhar7230]

Sir is there tutorial for verilog rtl for axi? If yes then please share link

[@Allaboutvlsii]

Not yet started

[@maharshitrivedi9545]

if you get the link please do share with me

[@shivamdwivedi5837]

SIr, can we get the ppt link for this tutorial? It would be a great help

[@maharshitrivedi9545]

did you get te ppt link please share with me

[@MSQ819]

you need to work on your explaining skill