Hello. First. Thank you very much for the lesson. Second. I have a question, I hope somebody could help me. When the current sources nmos transistors are clocked, the clock has digital levels? I mean, if the VGS is supplied by VDD, the VDS should be so high so they operate in saturation, or they could operate in lineal region? Regards.
Thanks for great lectures and I want to ask something. Can you re upload 9th lecture of circuit and system class. I am having difficulty to watch it. It is all green screen. Thanks again.
@@giblejess8983 Hi are you sure you have clear video after 2:30. Lecture begins perfect but then later on I am loosing the video. moreover for later minutes black screen turns into green. Which browser do you use? Thanks
These issues are often caused by the need for an updated player/driver according to the quick search I did on our future overlord (Google). I don't see any problems with that video either. Please let us know if the problem persists even after that.
@@AliHajimiriChannel I did extensive work - independent self-study - and am aware of deep technical issues; Resolves to common ordinary matters; It is that what is called _codecs_ → encode / decode; have budget at ( a brand ) then the encode-decode remains based on what I will call primitive code from decades prior which is developed in an early era; It will not get fixed I assure you; Were it to be that were so it would already be done;
11:31 Could you please explain the purpose of the PMOS latch? Why is it necessary to include it in the design?
I understand the positive feedback.
But is not there a way that circuit output not saturate rather sattles to intermediate voltages?
next level explanation skills
Hello. First. Thank you very much for the lesson.
Second. I have a question, I hope somebody could help me. When the current sources nmos transistors are clocked, the clock has digital levels? I mean, if the VGS is supplied by VDD, the VDS should be so high so they operate in saturation, or they could operate in lineal region?
Regards.
What is the use of Vref at the gate of tail current source ? Why Vref, why not any bias Voltage ?
12:20 it’s an attractive schematic style that drawing analog mosfets with arrows and digital mosfets with bubbles.
Thanks for great lectures and I want to ask something. Can you re upload 9th lecture of circuit and system class. I am having difficulty to watch it. It is all green screen. Thanks again.
Hi, maybe you can double check that since I actually can watch that video.
@@giblejess8983 Hi are you sure you have clear video after 2:30. Lecture begins perfect but then later on I am loosing the video. moreover for later minutes black screen turns into green. Which browser do you use? Thanks
These issues are often caused by the need for an updated player/driver according to the quick search I did on our future overlord (Google). I don't see any problems with that video either. Please let us know if the problem persists even after that.
@@AliHajimiriChannel Future overlord.. lol. Anyways, thank you for taking time to upload these videos into overlord repository.
@@AliHajimiriChannel I did extensive work - independent self-study - and am aware of deep technical issues; Resolves to common ordinary matters; It is that what is called _codecs_ → encode / decode; have budget at ( a brand ) then the encode-decode remains based on what I will call primitive code from decades prior which is developed in an early era;
It will not get fixed I assure you;
Were it to be that were so it would already be done;
Clearly explained, thank you sir!
thanks sir.......simply awesome...