125N. Two transistor stages: cascade, folded cascade, active load, Darlington, current mirror

Analog Circuit Design (New 2019)
Professor Ali Hajimiri
California Institute of Technology (Caltech)
chic.caltech.ed...
© Copyright, Ali Hajimiri

[@milindgoel405]

20:30 headroom explained.
28:00 small signal model is same for PMOS and NMOS
38:00 Ideal current source , ideal voltage source
41:00 MOSfet ends

[@tianmingguo8271]

Thank you so much!!! Great lecture. I was reading Darlington and the current mirror from different textbooks. Your explanations are the best and easiest to understand.

[@mortezaalavi]

Yet another impressive lecture, Now it is time for 21-century microelectronics, RF, and linear circuit textbooks which coupled your multimedia lectures to your original textbooks.

[@AliHajimiriChannel]

Thank you very much for your kind remark. I hope I have the time to develop it. Perhaps you can help me with that :-)

[@mortezaalavi]

Sure, My great pleasure, Always, and any time.

[@abdulladeeb5515]

More than fantastic... Your playing a sinfony ...

[@SJayanth]

58:43 Sir, isn't the bottom transistor already acting as a current source. What is the need of an additional current source on the top? This way, we have to connect the drain of it to some Vref to setup the current. Or is it just that instead of a Vref connected to the drain, you directly chose an Iref current source in series?
And very very thanks for the lectures. I bow down for passion of teaching and maintaining a great exciting environment in the class.
I never thought or heard circuit Design as an art before you described it many times in the class, previously I thought "all the equations, techniques, mathematics is established, simulators are there. What new can I add? But, now I see room for contribution for the variety of needs a circuit or system can demand.

[@clippotronics522]

this moment you messed up the exams at home university (other reasons ;D) and still so fascinated by this lecture. How can i get to the cal tech ??? :D :D

[@MrGyulaBacsi]

At around 9:00 you're writing for the output resistance for the MOS cascode as r_o = r_o1 * ( 1 + gm_2 * r_o2 ) but it's actually r_o = r_o2 * ( 1 + gm_2 * r_o1 ) isn't it?

[@星条旗ピエロ]

Sir, the video helped me a lot. But it seems that there should be another part in this class, but the next video is another chapter. If there is following contents or this class was over?

[@maxq4515]

There seems to be few mistakes in the calculation of the output resistances seen through the cascode stages. The expressions mentioned here are different from those derived in the last video.

[@rtv1196]

So, what about gm of the Darlington pair?

[@royalabhishekarya3143]

Is it possible to simulate folded cascode current mirror in cadence?

[@excitedbox5705]

How many cascodes do I need to get enough gain to read that tiny handwriting? :D

[@coolwinder]

It's just dense with information! :)

[@alpergirgin1]

nice shirt

[@caleb7799]

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