Razavi Electronics2 Lec15: High-Gain Differential Pairs, Intro. to Diff. Pair with Active Load

[@rahulchatterjee4177]

Arguably the greatest teacher of electronics

[@snehasuren]

Unarguably*

[@rahultheytv5347]

Thank you sir ,,, its very rare to find people sharing information with caring and no cost minds

[@coolwinder]

01:26 - Intro
04:00 - Differential Pair with Ideal Current Source Load
09:20 - Cascode Differential Pair
15:30 - Telescopic Differential Cascode Pair
23:37 - Cascode Differential Pair with Active Load

[@enesog]

At 33:02, if you cant see the green writing, make a snapshot, put it in paint and reverse the Colors, so you can see it easy.

[@bitvision-lg9cl]

Thank you sir, I understand what’s the potential means from this lecturer.

[@deepdivdivdeep]

Thank you very much for the precious teaching from sir.

[@amitgalkin1215]

best teacher! great insights!

[@mnada72]

Waiting eagerly for circuit theory I & II and the rest of the series.

[@qawasmi1992]

Razavi the Great

[@vimalkantpandey]

Thank you very much. When you are going to upload other videos of this series like Lecture 14 and others

[@vigneshrshankar668]

It has a name.. If you don't like the name, don't worry about it ! :D

[@devikaramesh1143]

😂😂

[@saisumanthnatva3560]

At 7:53, ideal current source should be replaced by a resistance (internal resistance of a mosfet, let's say ro3). So, gain will be -gm(ro1 ll ro3). Isn't it?

[@mazensayed3250]

it's called "ideal" because it doesn't have channel length modulation effect (ro)

[@dhirajkumarsahu999]

an ideal current source is a one, whose current always remains constant. That's why, while drawing the small-signal model, we replace it with an open circuit. (while drawing the small-signal models, we only consider small changes)

[@SAhellenLily]

CLM=0 and it means that ro infinity So Adm=-gmRd
Otherwise the CLM is not equal 0 and it means that hava a ro
Adm=-gm(Rd//ro)
rds=
ro=va/id=(1/CLM)/id=1/(id*CLM)

[@vaisnavashok930]

Why are the videos having an abrupt ending?

[@佳期又误]

When Delta V is small, the voltage at point P does not change. I totally agree with that. But, does that imply P is virtual ground? Yes, but why?

[@佳期又误]

I thought again and again on this. I guess my problem is still related with my incomplete understanding of biasing. P voltage does not change, it still has a voltage, bias voltage.. since this fixed bias voltage can be ignored in small signal analysis, point P can be treated as AC ground. I hope my guess is correct.

[@AmiraSlaiman]

Constant voltage => ac GND

[@noumanzia8808]

In cascode introduction we learnt that MOS transistor does not change the voltage with current like a resistor, but here we are making an opposite assumption. So are we treating MOS in triode region for active load?

[@brucemuller9205]

In differential pair with active load , when ID1 increases, ID3 increases, so ID4 increases due to mirroring...but ID1+ID2 = Iss which is constant...and ID2=ID4 so by this logic ID4 should decrease when ID1 increases.
Does it mean that M4 is in triode region?

[@sandeepmaurya5133]

Sir please do not use green color,it is not clear though.

[@varaprasadgrandhi8101]

Sir what is the difference between the regisitive load and current load. Because they are having same representation in mos diagrams.

[@shikharsrivastava8346]

42:24 please xplain,i didnt understand the 2 case

[@zaki5726]

in the second case consider the nmos to be a resistor if an increase current has to flow through the nmos then the potential drop across it will be higher , hence v out will be higher

[@abhishektyagi7513]

@@zaki5726 I agree but think like this, to maintain the nmos in saturation Vds>Vgs-Vt. In the first case, Vgs of the lower nmos is rising as more current has to be pushed through due to current mirror action. If Vgs increases, then so should Vds to maintain the pinch off condition. This is opposite to what I will get if I consider the loading mos as a resistor where a current increase will just give a greater potential drop across it and thus Vout will drop. I am confused. Can someone explain where I am going wrong?

[@dhirajkumarsahu999]

@@abhishektyagi7513 if the Vgs of the lower nmos rises (which rises due to more current due to the action of the current mirror), it does not imply that the Vds should also increase. In fact, with the increase of voltage between the gate and source, the voltage between the drain and source decreases. That's why it acts as an inverter. You would also have observed, its gain is given =-gmRd( negative sign indicates inverted output).
This can be explained as follows- as the voltage at the gate increases, the channel gets more enhanced with the charge carriers. This results in decreased resistance of the channel, and hence the Vds decreases.
I hope this will clear your doubt.

[@shubhamnayak9369]

@@dhirajkumarsahu999 but you see.. when I increases, Vgs of Ma increases so Vgs of Mb also increases and as Mb is CS stage so Vo should decrease. But here it's something else is explained

[@oakspines7171]

We use active load instead of passive resistor.

[@askago4884]

Make me strong you sir ........

[@توكعزيزة]

Really thank you .

[@kunalvatwani9535]

So basically m1 wants id1 to increase which increases id2 so Vout increases
And M2 wants to decrease id2 so that Vout increases.
id2 both increases and decreases and in both cases increases Vout??????
Something seems wrong

[@Priyajit_Ghosh]

I think superposition is taken here.
1. Vgs of M2 dec -> Im2 dec -> now think M4 as a resistor, -> Vdd - IdRd = Vout - > Vout inc
2. Vgs of M1 inc -> Im3 and Im4 inc-> think M2 as a resistor -> Vout = IdRd -> Vout Inc

[@juelzpole1783]

So kiiiind. Thank you

[@amitkumar-sh2lk]

Sir please dont use light green colour for writing as it is not visible . istead u can use dark green colour

[@mhmd_rjb]

47:34 P can't be ac ground anymore

[@mrpossible5696]

43:10

[@hardikjain-brb]

42:32 beautiful