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No one can teach elecronics this clearly , you really made this easy. THANK YOU SIR...😇

And why we don’t take output voltage from RL resistence??49:32

Everything is explained so clearly. Master teacher.

At 37:28, for cap discharges, should that be negative charges(electrons) go from the negative plate to the positive plate clockwise? I believe charges can not flow between the plates.

the best ever prof. in the earth

I m from uiet kanpur ECE STUDENT

I love purple 💜

at 47:20 which battery is drained Vds or Vgs

Utkarsh Pant: This is outdated crap. Remove it. A more updated series by Razavi is posted by Mohammed Abdelbaset. That is dated 2020.

god level explanation

Thank you so much Sir. The lecture was fully understandable especially your smile at the end of each lecture 😻

Hello sir in quiz at 51:00, you connected mosfet to positive terminal which indicates a positive feedback so the concept of virtual short may not work i.e. Volt at inv terminal won’t be same as non inverting terminal and opamp operates in saturation region right?

Fucking amazing!!

I just found out about this series 8 hours before my exam and now im doomed

These videos saved me. thanks

Holy this is mad hard, need to rewatch these videos twice. Great teaching, i'm just a bit slow lol

Greetings from Türkiye 🇹🇷 Hocam you are the best in electronics!!!

best prof in milkyway galaxy,thank you

thank you Sir 👍 Simple coepect 😊

Question at 49:00 "Prove that the mos device always turns on in saturation if VDS > 0?" Answer: In a MOSFET, saturation mode (or active region) happens when the drain-source voltage (V_DS) is greater than the difference between the gate-source voltage (V_GS) and the threshold voltage (V_T). Mathematically, it’s when: VDS > VGS - Vth When VDS exceeds this threshold, the channel at the drain end gets pinched off and the current is no longer dependent on VDS but rather on VGS. Simply put: 1. For VDS > 0, the device can either be in the linear region or saturation. 2. For it to always be in saturation, VGS-VT would need to be zero, which is not realistic in all operating conditions. So the key is VGS>VT & VDS > VGS - Vth. Without those conditions being met, VDS > 0 alone doesn’t guarantee saturation.

Incredibly beneficial lectures. Thank you

is drain and gate is connected or drain or source

🫶 very Simple conpect at5:29 Ldo model circuit of voltage regulator 🤔 -ve,Negative feedback with R1 and R2 at 6:20 RF circuit Why no applications circuit introduced ?😮‍💨

When we look at the ID (Drain current) vs VGS (Gate-Source voltage) characteristic: 1. For VGS < Vth (threshold voltage): - The device is in the cutoff/subthreshold region - Very little to no current flows 2. For VGS > Vth: - A channel forms - If VDS > 0: - There will be a potential difference between the drain and the source - This causes current to flow through the channel - The device enters saturation when VDS > (VGS - Vth) - In saturation, ID = k(VGS - Vth)²/2 Therefore, to prove the device "always turns on in saturation if VDS > 0": - Once VGS exceeds Vth, a channel forms - Any positive VDS will cause current to flow - As VDS increases, the device naturally enters saturation - The key is that VDS > 0 ensures there's a driving force for current flow, and the quadratic relationship between ID and (VGS - Vth) in saturation ensures the device is "on."

please add some playlist for electronics 3 course

i request to sir to add some more videos in this youtube channel so for that some poor student willl get sucess.

yes sir is explaning like a giant.actually he is the giant of electronics

Hello professor, in iitd we use your textbook. I used to believe you would be more complicated in teaching than my college professor( just like the complexity of your book..lol) , now I come here to understand what my college professor actually taught me in class🙂🙂🙂

یک جهان ممنون داکتر صاحب

30:04

Who is from India ❤❤❤

very good to start CH3

Thank you🙏

Goat!

35:00 NO HELP YET!!!! What he says about current going in equals current going out makes sense. But the dependent current source other than 1 to 1 (no gain) will not follow KCL. The extra current has to come from somewhere. The formula will only work if K is reversed logic. Example, K being positive with the other drains (I1+I1R1/R2+KI1,,,etc,,) or negative when moved left of the equals sign. PLEASE, if anyone else has tried this example, let me know what worked out for you! Thank You MGM

Thankyou sir

Can anybody tell me is it enough to prepare for the exam ?

35:00: Everything I know, I learned from the "Great B". But, I'm still learning, and this drove me nuts for a few days. Please let me know if making K should have been "negative" on left side of = sign. It is the only way it works out for me. I tried the math and many simulations to prove it out. Is False: Ix+KI1 = I1+(I1R1/R2)+ (I1R1/R3+R4||R5)+Iy Is True: Ix-KI1 = I1+(I1R1/R2)+ (I1R1/R3+R4||R5)+Iy Also True: Ix = I1+(I1R1/R2)+ (I1R1/R3+R4||R5)-KI1+Iy => Ix-KI1 = I1+(I1R1/R2)+(I1R1/R3+R4||R5)+Iy Finally "I1" I1 = Ix-Iy/(I+(R1/R2)+ (R1/(R3+R4||R5))+K) Thank You for any help! MGM

Thank you for lecture. blessed that i can listen to one of the greatest lectures from the other country

Dude cramming all this 2 days before the exam is not it 🥲

EXjYu7_€🇨🇮🇦🇷🏢🇸🇭

Excellent Lecture Professor Razavi, Thank You.

These lectures save my midterm and they will save me again in final

젠장 라자비는 신이야

The Quiz music is painful.

30:24 will not the current also vary a bit I mean the current also will become Iee/2+del(I) and Iee/2-del(I) in this circuit. So the Vx and Vy also should change

12:00 "C" by itself is Uppercase; "c" in "coulomb" is Lowercase.

Bu dava sensiz olmaz

In cascode introduction we learnt that MOS transistor does not change the voltage with current like a resistor, but here we are making an opposite assumption. So are we treating MOS in triode region for active load?

Thank you so much for teaching such a clear and systematic approach.