I approve of Dr. Hajimiri's emphasis on familiarizing one's self with the various topics and effects in a way that's "conducive to design." I believe in exactly the same thing - I phrase it a different way. The goal is to get to the point where you can design "intuitively" in your mind. Obviously you don't work out every numerical value in your head, but when you can do this you can consider and discard (when appropriate) design options. The early phase of your design process - while you're "arriving at an architectural plan" can just be done... "contemplatively." Analog wasn't my specialty - I'm not at that "intuitive" level in analog design. But I can do it with digital logic circuits, and it's a very nice feeling being able to do that sort of thing.
12:00 body effect 27:30 source degeneration reduces gain to make circuit but reduce output swing,lesser headroom and increases output resistance 37:00 Second order effects in % definition 46:00 diode connect load , load-line vs resistive load-line
If in small-signal model most of the Is1 flows trough Rmb, does that mean that when we look at large-signal model, the change in Vin will almost not have an a effect on Ic trough the Re (DC component of Vin is constant)?
Hello sir Here is one question that bothered me about the biasing of pfet, if we apply higher than 0.7 posstive voltage at source terminal then pn Junction that formed between source and bulk would have forward bias and could damage the transister because of huge diffusion current if bulk is grounded which is normally the case. Can you please clear my concept here.
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I approve of Dr. Hajimiri's emphasis on familiarizing one's self with the various topics and effects in a way that's "conducive to design." I believe in exactly the same thing - I phrase it a different way. The goal is to get to the point where you can design "intuitively" in your mind. Obviously you don't work out every numerical value in your head, but when you can do this you can consider and discard (when appropriate) design options. The early phase of your design process - while you're "arriving at an architectural plan" can just be done... "contemplatively."
Analog wasn't my specialty - I'm not at that "intuitive" level in analog design. But I can do it with digital logic circuits, and it's a very nice feeling being able to do that sort of thing.
12:00 body effect
27:30 source degeneration reduces gain to make circuit but reduce output swing,lesser headroom and increases output resistance
37:00 Second order effects in % definition
46:00 diode connect load , load-line vs resistive load-line
thank you
I am indebted to Hajimiri sir for his wonderful explanations.
If in small-signal model most of the Is1 flows trough Rmb, does that mean that when we look at large-signal model, the change in Vin will almost not have an a effect on Ic trough the Re (DC component of Vin is constant)?
Hello sir
Here is one question that bothered me about the biasing of pfet, if we apply higher than 0.7 posstive voltage at source terminal then pn Junction that formed between source and bulk would have forward bias and could damage the transister because of huge diffusion current if bulk is grounded which is normally the case. Can you please clear my concept here.
For pfet, bulk is connected to highest potential available, which is vdd in this case
Is this masters level course or bachelor's level course
Masters, he says in one of the prior videos "As graduate students of CalTech"
@@krisk3452 both