What confuses me is why we dont see this vast improvement between the 5900X and 5800X, considering that the 5900 has 32MB shared between 6 cores and a total of 64MB shared with 12 cores, whereas the 5800X shares 32MB with 8Cores. 5900 has 5.3MB per core, and 5800 has 4MB per core So per core, the 5900 has more cache per core and so we should see some sort of uplift but we dont.
If you play 1440P or 4k with highest SETTING. You won't able to see difference. GPU 3D cache makes a difference. But having bigger cache in CPU is nice.
@@LightMCXx AMD gave an average uplift for this CPU based on 1080p gaming, which is a 15% uplift. That's a pretty good jump and making a claim that you won't notice a jump when moving to 1440p gaming, when you have GPUs right now that are much better that last gen GPUs, AND you have technologies like DLSS 2.0 and FSR 2.0 that increase the graphics performance, I'm going to flat out say you're wrong. Yes, if you have a GPU that craws like a turtle at 2K gaming you're probably not going to see any difference, but then I don't know why you'd go out and buy this CPU considering Zen 4 is about to come out and Alder Lake and Raptor Lake are also really good at gaming So one still has to use some common sense when buying hardware. I would say if you don't already own an AM4 platform that's worth keeping for a long time because you spent a lot of money on it (X570 MB, 32GB DDR4 DRAM), this isn't a good buy. But, if you built an AM4 platform based on a high quality X570 MB that is 100% PCIe gen4 BTW, and you've bought a high quality GPU, this makes sense if you're idea is to have it for years. DLSS, FSR and RSR will get better which speeds up graphics processing, and that then means even 2K gaming will easily benefit from this when you have a REAL 2K gaming GPU, such as a 3080 or 6800 or better. For 4K gaming, well, all I can say is the game better have DLSS or FSR because there's only a small number of GPUs that can game at an fps that most gamers would want to play at anyway. Personally I wouldn't even consider 4K gaming for about 2 more generations of GPUs, when I think there will be a good 4K gaming GPU that can actually run using less than 300W. But that's just me personally because my PC is in the same room and I don't like having to strip down naked to run a GPU that's using 400W while I'm gaming for a couple hours. I mean that's starting to get near a low setting for a space heater. Throw in the CPU and other components and you're actually running a space heater, but instead of a thermostat controlled device, the thing is constantly putting out heat. No thanks. Even my 2K gaming rid with a 6800 XT starts to warm up the room, and it's using less than 300W. But the same thing applies. If you have a GPU that's good for 4K gaming, AND the game includes DLSS or FSR, whichever your GPU uses and this then gets your fps up a bit higher, then this CPU will make a difference. It won't be as much as 1080p gaming.
@@johndoh5182 Yea and PCIE 4.0 not that bad for 7000 series amd or nvidia GPU, unless if the GPU 5.0 8x lane (entry level card) or upcoming SSD. DDR5 is nice but didn't give much improvement and DRR4 still last many year to come like DDR3. for CPU Me gonna go for 12600k or 12700 for streaming , gaming with 32gig ddr4.Also 1tb SAMSUNG 980 Pcie 3.0 ssd.
@@LightMCXx I'd say it makes a huge contribution for future-proofing. Sadly I'm still on ancient i5-4460 which is showing serious cache defficiencies. Especially as I've always opened 25-30 Chrome tabs and bunch of other stuff opened simultaneously, 6MB of L3 cache is not enough for 2022...
AMD please do more of these kind of educational video's it's really interesting! Maybe one day a tour behind the scenes? I'd love to see the design process of a CPU, the R&D departments and such
Freaking love this series, Robert explains it so cool, makes super complicated tech into easy to understand concepts for us, the consumers. Loving my switch from Intel to R5 3600 and soon 5600
Actually interesting, great video AMD, please make more! Edit: there's no better way to promote a function than explaining it and giving the customer knowledge
no wonder why he is the Director of Marketing, i haven't seen any likeable marketing personality like him, the video is around 10 mins, usually i feel bored and dont go through such videos till the end, but with this guy, i just want more content and 10 mins just feels short. we should get more videos about AMD techs done by Robert.
The fact that AM4 lasted a decade is exactly why I was able to be an early adopter of AM5. Decade-long sockets with respect for compatibility is HUGE. Keep that focus on compatibility and people will love your product.
i wish they cold tell us more about how they got to "hybrid bond 3d" like how they made the conductors so much smaller and denser. sadly we probably want get that story for a another 10 year's or more
That's called HIGHLY classified IP at this point. Yeah, you'll probably never hear how this is done for a few more years. But I guarantee you that some entity in some country is trying to hack into TSMC systems to get a hold of this IP.
@@TheMakiran that is AM5 that means new system which also mean NO!! A 5950X3D is a drop in replacement and what i both want and need to exist otherwise its the 5950x and that is a piece of crap in comparison to what a 5950X3D would be
@@TheMakiran yes actually it does because of my use cases We are talking about the 5950x and a 5950X3D and so it should instantly be presumed i am not just some one that watches videos and plays games and thats all otherwise a 5600x fits perfectly for that I need the cores of the 5950X, i need the Cache of X3D and i need the per core performance which also ties into the Cache size as it accelerates what i do and better uses the clock cycles For my use cases it’s more like a 40% increase over a 5950x
Thank you for this presentation. It was very interesting. In regards to shaving the die portion, does that not reduce effectiveness of the remaining die? How is it able to match the performance of an unshaved die? And if there is no difference between the two then couldn’t we increase the output of usable dies by vertically splitting them? You can even hybrid bond them back if it isn’t a two to one ratio.
Chips are not 3D. The usable transistors are just on one surface of the entire die. The rest of the die is completely without function, just a block of silicon. People have been thinning dies forever by sanding them. Extreme overclockers do this to reduce the distance the heat has to travel through silicon and get to the cooler, hoping for better temperatures. They call it die lapping. You can theoretically shave it down to just a few atoms thick, but you know from larger scale experiences in your own life how hard it is to make something thinner without breaking it.
@@BSEUNHIR Well not exactly on one side, the interconnects are, but the actual transistors are inside, and you can thin it too much and damage the transistor layers. Die thinning is a really dangerous thing, must be perfectly flat, not too shallow and not too deep.
Intel did their own die shaving back on 10th Gen K SKUs. For them however, it was as a heat management measure. The thinner die allowed for the heat to escape faster.
@@blkspade23 But this wasn't die splitting because you have 2 horizontal layers of transistors to produce 2 separate die on that same layer of silicon.
The explanation is very extensive yet super simple at the same time, so it's much easier for a person like me that knows nothing about this technology to actually understand it, just one question tho, how are you be able to write backwards ?
Thank you robert for explaining it in such an easy format. We need more such videos for everyone to have some basic knowledge about the products they are planning to buy. I hope amd will be able to provide us with some unlocked 3d v cache cpus soon after this, possibly with zen 4 or zen 5. That would be the icing on the cake.
That is surely something they can test with heat cycles and would not worry about that, probably the same silicon quality is used to minimize the heat induced stretching. But what has to be considered is that another die on top will consume power. And this is why the X3D has 200 Mhz lower clocks compared to the standard 5800X, in order to maintain the same TDP and heat output, and also the heat of the CPU die itself need to pass through the cache die to get cooled, so they might have problems with higher heat on the CPU die itself - overclocking could damage it easier.
Would have been awesome to provide more details than this surface level explanation. How exactly do you make the die connections? How do you handle the heat output?
Hbm memory amd Hbm from 10 year's I loved the explanation thank you , it can be used on everything like i already guessed since it already as been an adaptation. My next machine will arise from your old ashes it will show things clearly i swear
I work in Aerostructure manufacturing and I'm familiar with what you're talking about called: "Wringing" where 2 very flat parts placed together interchange electrons through molecular attraction 🧲 but there's no magnetism involved! We do this daily 😌
I speculate this legendary CPU is going to show it's true potential in the next 2-5 years when GPUs would become roughly 2 to 4+ times faster than what they are now. For now almost all GPUs will run at almost 100% utilization at all common screen resolutions when you pair them with this CPU and this is the reason users might not see the big difference today when you compare this system with other CPUs like Core i9-12th gen something. The reason for this is high core and clocked non-v-cache Zen 3 CPUs have already pushed current generation GPUs to its limit. Because in theory (and I don't see a reason why that won't be in practice), 3D-Vcache based CPU should be capable to draw bazillion times more draw calls than what is currently required to push the current gen GPUs. I predict the difference between say Core i9-12900k no matter the overclock (6 GHz? doesn't matter) and stock 5800X3D is going to become progressively larger as the time goes by (with 5800X3D keeps approaching more and more frames per second). Date: IST 29-March-2022 - 07:02 PM
unfortunately by that time, better IPC from zen5 beyond as well as wide adoption of ddr5 will have exceeded the performance of this chip. Bottomline is, it needs to perform NOW, much like the competition is doing. But hey, if that is indeed what will happen, then good for those who are planning to buy it now and plan to keep it for multiple years without upgrading. It is indeed the best and last hurrah of the am4 platform in terms of gaming after all.
You are not considering that latency is not the only limitation to memory access. There is also the bandwidth. So I guess faster DDR5 with lower latencies will alleviate the cache advantage, even though today it does not do much still, similar to how DDR4 2100 was barely matching the latest DDR3.
@@marsovac I bet $100 that the DDR5 of next 4 years won't reach L3 level latency of todays CPU. It's almost physically impossible in current paradigm . Unless we would have option for installing DRAM chip size of a quarter of a nail or something like that into the CPU die itself, it won't happen. You will need DDR5 10000 MT/s in quad channel to reach the L3 bandwidth of 5800X3D and even then memory latency will be at least 5 times slower with DRAM. Not only that, read and write transfer between L3 and other CPU cache is simultaneous. It means many read and write operations can happen simultaneously. Afaik DRAM either does read or does write operation at a time.
@@deleater It never will, but it can make up for it with frequency/bandwidth in respect to the DDR4. The same latency thing happened with DDR3 vs 4: CAS 9 vs today CAS14, and still DDR4 is now noticeably faster than DDR3 ever was. My point is that upgrading the memory on a 12900K to some fast DDR5 might offer it scaling that the VCache will give today. Although the VCache does not cost as a memory upgrade, so it perfectly makes sense if you want to upgrade today an old ryzen system with the X3D, especially since DDR5 is not an option for current gen AMD.
4:50 Does anyone know what exactly this process is called? Would love to just read about this at night instead of sleeping. Is this the same process called cold welding where two metals that aren't oxidized would weld together if they touch in vacuum?
Been thinking about 3D VCache and I have a question! Wouldn't it be a good idea to implement the cache chip in reverse? By this i mean having a "trench" on the substrate where you place the cache chip and then put the CPU chiplet on top of it instead of the cache on top of the CPU, you could possibly even then have 2 cache chips, one above one below, though my idea here is to avoid the heatspot issues by having the cache below the CPU chiplet to enable the CPU to be directly next to the heatsink instead of adding distance and thermal "soaking" areas with the current approach.
I am guessing it would be too difficult to get interconnects going through/via the cache to the die on top and there would a latency penalty from having the die further from the substrate. An interesting idea though.
@@Je-kg8up the distances remain pretty much the same, in fact could improve with die thinking which would be a good idea to do as the cache does not get as hot as the cpu, so it can really be thinned without much thermal considerations, a this point the structural integrity would likely be the limiting factor.
It might be harder to manage the heat from a system like this, however if theres a massive nearly generational leap in performance then as long as its similar in heat output to the rest of the Ryzen family I dont see why there would ever be a need to overclock the chip.
if your calling the vcache L3 and not L4 is this type of L3 not slower than on die L3? I assume it is, but because your stacking it on top it gives you alot more L3 compared to before which it's benefit is you stop fetching from RAM
@@malathomas6141 yeah that's what I was thinking, The stacked cache used as L3 is just a little slower than standard on die L3 but because you can have twice as much or more cache in comparison to standard on die L3 cache the system can work faster because it's not fetching as much from RAM.
They're Chiplets, but they decided not to stack the memory on these first cards. It's very possible that their 7950xtx or whatever they will call it has that. But apparently they didn't feel it needed that boost for the price to add it.
June 2024. I got a whole new internal PC parts including case. I bought an AMD Ryzen 9 7950X3D 16 core CPU. Just remember to install the AMD Adrenaline Software. It will install the two AMD 3D V-Cache Optimizer Services to run in the RAM to make V-Cache always active when it needs to work.
Guys please don't become intel like monopolist that makes unsustainable pricing on your products we love amd for what this is and we love technology that stays behind it
I am pretty much sure AMD will use 3D V-Cache in the next gen and probably even upcoming PS5 Pro consoles. 3D SRAM cache will be a key player in the future and will play significant role not just in the gaming CPUs especially when SRAM is for now not going to be shrink even further unless new type of transistors r adopted and widely used.
I am telling you, I have had AMD for years now for gaming and for me it is way better than Intel. I have a desktop with a Ryzen 5, RTX 2070 Super, does pretty good. Laptop with a Ryzen 7, RTX 3060 that does better. Just researched today and found out my desktop can handle a RTX 4090, so next month I will see what life is like with that and a 8k OLED. Christmas I will teat myself to a new something with what he is talking about. Excellent video, love science.
As the Chair of the IEEE Semiconductor Roadmap ( IRDS ) Packaging Integration section and a 30+ yr veteran of developing Advanced Packaging technologies and their transition to High Volume Mfr. ( not just for Micro Processors and Smart Phones - both digital and RF but also for HBM / HMC & SuperComputers, my inventions now amount to over $30 billion / yr of Semiconductor production worldwide ), I must TAKE EXCEPTION to AMDs PUFFERY. Shame on Lisa Su who used to be a jr. PhD ( hired from MIT ) at Motorola where in the '90s ( when neighbor AMD was virtually DEAD ) we were doing most of this work, for letting people under her getting carried away w/ their FLUMMERY. Neither AMD nor its offshore Foundry are the inventors or first users of either micro Pillar ( invented in 1994 by yours truly at Moto, by 1996 in Moto FlipPhones out of a fully Robotic line in AZ which too I had to design & develop ) or Hybrid Bonding - Copper ( HBC, invented by Paul Enquist of Ziptronix, NC around 2011, in use by 2017 at SONY in Cameras for SmartPhones ). SONY too was the first to split up one large Camera Chip that had included both the Imaging and the Processor sections ( requiring finer node mfr. into 2 parts and connecting them by HBC ) thus cutting cost. In terms of process capability SONY still leads AMDs offshore Foundry ( whose capability is described in the Video above ) when it comes to the "pitch" ( spacing ) of their HBC connections by over 2X. The same concept is now applied to V cache by taking the hard to shrink SRAM out of the Processor. And BTW the Dutch Physicist ( whose 100 yr old principle was used by Paul E. to develop first DBC and then HBC ), that the AMD presenter refers to as mere Johannes ( perhaps because that was all he had been supplied with by their PR dept. ! ), is better known to any Science or Engr. undergrad as Van der Waals. The force that sticks the hybrid part of the die to die bond ( btwn the dielectric INSULATING covers on the two dies ) is called van der Waals force. But the actual CONDUCTING bond btwn the two dies on the mating Copper pads sticking out through the insulator layers takes place by a Metallurgical process called Grain Growth and Twinning. For that to happen in a reliable way, first the dies and wafers to be bonded by HBC have to be prepared by quite finicky pre processing called CMP.. The actual lP for the DBC / HBC process is now owned by a 30 yr old US HQed Packaging tech / licensing Co. in Santa Clara, CA called XPeri. After all this hoopla the improvement in electrical performance ( bandwidth, throughput, power eff. ) w/ V cache is around 12%. In contrast a British start up has come up w/ AI chips ( incl. Accelerators ) also using HBC and fabricated at the same offshore foundry, BUT w/ a more intelligent electrical design shows an improvement in AI Benchmarks for Training & Inference of 40% !
Lux the Droid robot loads fast enough loaded in 300MB's of CACHE ^p Say 700FPS The size issue is not one clearly defined by progress, but defining reality though pre tested hardware? Source of future security & reliability RS So Security 'LUX' The DROID : Really does float in 32MB floating L3 RAM Tables
I'm imagining the AM12 with Pyramid Stacking technology. A Pyramid shaped CPU that requires a cone shaped cold plate to allow huge 3d stacked chips. Cache in the centre and cores around the top so the centre isn't as thermally dense.
Wait but it just explains the importance of l3 cache but doesn't explain the importance of having a 3d v cache. So a traditional l3 cache with 96mb vs a 3d v cache with 96mb
Closely have to explore 3D V-Cache, knowing AMD is always innovating, one chip in hand of that kind would be evident whatever the benchmarks are stating
I own rtx 3090 and play games at 1400p but the GPU is never pegged at 99%. It is fluctuating from 60% to 90%, this makes my games run like crap. I need a cpu with at least 2x the ipc than the i9 9900k I have.
I wonder if they have done shock/drop tests to make sure the bond doesn't break from the stack. It needs to be made Linus proof. Physicists can chime in if you know what you know.
Hey Robert, we still wait for a CO fix on the 5000 CPUs, you know, that BSOD on low load/idle after standing 20 hours tuning it on high load and stuff… any news on that or we have forgotten about that feature? You know that feature that was at least 30% of the reason ppl bought the CPU.
Ugh... I could've used a bit more of a deep dive. You basically just said what was already said at Computex. You just said it a little slower than Lisa did :P
if the cpu cores are going to be below and the memory on top will the cpu cores be cooled from beneath the motherboard? or could the memory be below with the cpu cores on top so that the cpu core are cooled from above the chip? maybe question is more relevant if it's many layers of memory and other stuff on top of or below cpu cores
I'm curious how they'll tackle heat with different dies on dies. Perhaps some of those interconnects could be dummied out for solely heat transfer and soldered to an intermediary layer of copper that contacts the IHS? Do I dare entertain the thought of AMD et al carving grooves into their dies and filling them with water???
@@sonpham4119 For the 5800X3D this is true. AMD sent a notice to motherboard manufacturers to disable overclocking for the 5800X3D. I think in response to an inquiry by Gamers Nexus?, AMD said the reason for that was something about the Vcache needing strict adherence to 1.35V. And to stay within the same 105W TDP as the original 5800X, they reduced the 5800X3D's clocks to make up for the power draw of the extra cache. They also said that this was solely limited to the 5800X3D, indicating that they already solved the issue but just didn't have time to engineer it into the 5800X3D...?
@@mahatmagandhiful If what the other person said is right (about cache and CPU cores both drawing from VCore), then AMD would not have been able to implement it into the 5800X3D at all, as it would require extra separate power lines that the existing socket AM4 motherboards do not have, requiring a revised socket and new motherboard. Remember, one of the points of buying this CPU is so you can get one last performance boost on your existing AM4 motherboard instead of having to replace it too. The AM5 socket and AM5 CPU packages have many, many more pins than the AM4 socket has, and a number of those pins are likely the separate power deliveries for the cache if what was said is true.
That's because of all the thousands of lines of code and data that a program or game may store on the CPU cache and RAM, not all of it is accessed at an equal rate -- never. Some chunks of memory are accessed literally millions of times per second, while other chunks of memory may only be accessed on a lesser frequent scale, i.e. thousands of times per second. The bits of memory that are used the most frequently are stored on the L1 cache of the CPU, which is the fastest and lowest latency cache. Bits that are accessed frequently but not nearly as much as the most accessed, are stored in the L2 cache. The rest of the frequently read code is then stored in the L3 memory, and everything else gets stored in the memory of course. L2 cache is slower and higher latency than L1, L3 is also even slower than L2 and higher latency, and of course, the RAM is the highest latency and worst speed of all. RAM is always slower than cache. By having a larger L3 cache size like with the Zen 3 3D V-Cache CPUs shown in the video, more and more of those frequently accessed bits of data, that would have been stored in RAM since the cache was full, are stored in the larger L3 cache instead, providing a performance boost to the application, depending on how memory-intensive the application is (in terms of data speed, not data capacity). It doesn't matter how much memory the program uses, a program will always have very often used bits of code, as well as code that isn't nearly as used often, with the difference between the two being orders of magnitude. More RAM will only speed things up if the program was using enough RAM that there was very little/no free memory left and page ins and outs to the pagefile on the HDD/SSD had to occur because of it. An SSD may be very fast compared to a HDD, but an SSD is still hundreds to thousands of times slower than memory, both latency and bandwidth wise. Hierarchy of cache/memory speeds and latencies: L1 > L2 > L3 > System RAM > Pagefile.
@@bestage9429 Thanks you for such detailed mini-review of interaction between CPU cache, RAM and SSD/HDD. I'm not a programmer/technician and one thing I cannot understood - how CPU decide what code it will place in L3 cache and what will be in RAM? (hypothesis is that CPU has it's own algorithm? or it's not how all works...). P.S. Sorry for my English, I'm from Ukraine🇺🇦 and don't know English well 😔
@@Charodiy_UA This one is a bit of a complicated question to answer for me, but basically there are algorithms and logic in the CPU to determine what bits of memory will be placed in L1 cache, what will go in L2, etc. One such algorithm is called prefetch, where memory access patterns are used to predict what blocks of memory will be needed next, and store them in the cache.
@@bestage9429 It's really interesting 👍, now I want to read more about this complicated process and will learn more to know how all this communication between CPU, RAM, SSD, Videocard work and of course what role take Motherboard in it!
You could place a small plate of synthetic diamonds, since they have a higher thermal conductivity and those that are made by machine are cheap. the best ihs would be that
Robert always exceed himself explaining this. GG
The no glue part is amazing!
Sounds like cold welding
I hope you make a 5950X3D if this ones successful, we need an ultimate high-end 3D flagship for the X570 playform.
What confuses me is why we dont see this vast improvement between the 5900X and 5800X, considering that the 5900 has 32MB shared between 6 cores and a total of 64MB shared with 12 cores, whereas the 5800X shares 32MB with 8Cores.
5900 has 5.3MB per core, and
5800 has 4MB per core
So per core, the 5900 has more cache per core and so we should see some sort of uplift but we dont.
5900X has two core complex dies. The latency introduced from that is the problem.
Bye bye Intel.
He works at intel now lol
Really happy with my decision to give amd a shot. I bought the 7800X3D and I LOVE the performance
Robert, this was great. We need more up-close lessons like this to inform the masses. Great and informative video.
I'm not too knowledgeable when it comes to this processor cache stuff, so this was interesting and simple enough to understand, nice
If you play 1440P or 4k with highest SETTING.
You won't able to see difference.
GPU 3D cache makes a difference. But having bigger cache in CPU is nice.
@@LightMCXx AMD gave an average uplift for this CPU based on 1080p gaming, which is a 15% uplift. That's a pretty good jump and making a claim that you won't notice a jump when moving to 1440p gaming, when you have GPUs right now that are much better that last gen GPUs, AND you have technologies like DLSS 2.0 and FSR 2.0 that increase the graphics performance, I'm going to flat out say you're wrong. Yes, if you have a GPU that craws like a turtle at 2K gaming you're probably not going to see any difference, but then I don't know why you'd go out and buy this CPU considering Zen 4 is about to come out and Alder Lake and Raptor Lake are also really good at gaming
So one still has to use some common sense when buying hardware. I would say if you don't already own an AM4 platform that's worth keeping for a long time because you spent a lot of money on it (X570 MB, 32GB DDR4 DRAM), this isn't a good buy.
But, if you built an AM4 platform based on a high quality X570 MB that is 100% PCIe gen4 BTW, and you've bought a high quality GPU, this makes sense if you're idea is to have it for years. DLSS, FSR and RSR will get better which speeds up graphics processing, and that then means even 2K gaming will easily benefit from this when you have a REAL 2K gaming GPU, such as a 3080 or 6800 or better.
For 4K gaming, well, all I can say is the game better have DLSS or FSR because there's only a small number of GPUs that can game at an fps that most gamers would want to play at anyway. Personally I wouldn't even consider 4K gaming for about 2 more generations of GPUs, when I think there will be a good 4K gaming GPU that can actually run using less than 300W. But that's just me personally because my PC is in the same room and I don't like having to strip down naked to run a GPU that's using 400W while I'm gaming for a couple hours. I mean that's starting to get near a low setting for a space heater. Throw in the CPU and other components and you're actually running a space heater, but instead of a thermostat controlled device, the thing is constantly putting out heat. No thanks. Even my 2K gaming rid with a 6800 XT starts to warm up the room, and it's using less than 300W. But the same thing applies. If you have a GPU that's good for 4K gaming, AND the game includes DLSS or FSR, whichever your GPU uses and this then gets your fps up a bit higher, then this CPU will make a difference. It won't be as much as 1080p gaming.
@@johndoh5182 Yea and PCIE 4.0 not that bad for 7000 series amd or nvidia GPU, unless if the GPU 5.0 8x lane (entry level card) or upcoming SSD.
DDR5 is nice but didn't give much improvement and DRR4 still last many year to come like DDR3.
for CPU
Me gonna go for 12600k or 12700 for streaming , gaming with 32gig ddr4.Also 1tb SAMSUNG 980 Pcie 3.0 ssd.
@@johndoh5182 However my motherboard have PCIE 5.0 and sightly 10 dollar pricy than mortar but worth it for my need.
@@LightMCXx I'd say it makes a huge contribution for future-proofing. Sadly I'm still on ancient i5-4460 which is showing serious cache defficiencies. Especially as I've always opened 25-30 Chrome tabs and bunch of other stuff opened simultaneously, 6MB of L3 cache is not enough for 2022...
This is a master class in making technical information accessible. Bravo!
AMD please do more of these kind of educational video's it's really interesting!
Maybe one day a tour behind the scenes? I'd love to see the design process of a CPU, the R&D departments and such
Freaking love this series, Robert explains it so cool, makes super complicated tech into easy to understand concepts for us, the consumers. Loving my switch from Intel to R5 3600 and soon 5600
can wait for am5 stuff , just waiting for them to release zen4 and i am jumping to them
Welcome to team red
Actually interesting, great video AMD, please make more!
Edit: there's no better way to promote a function than explaining it and giving the customer knowledge
no wonder why he is the Director of Marketing, i haven't seen any likeable marketing personality like him, the video is around 10 mins, usually i feel bored and dont go through such videos till the end, but with this guy, i just want more content and 10 mins just feels short. we should get more videos about AMD techs done by Robert.
The 5700x3d is so fast! Good job AMD!
Your video worked, I bought a 5800X3D at launch from Newegg. Congrats!
This man is amazing i love the way he explains it all
The fact that AM4 lasted a decade is exactly why I was able to be an early adopter of AM5. Decade-long sockets with respect for compatibility is HUGE. Keep that focus on compatibility and people will love your product.
i wish they cold tell us more about how they got to "hybrid bond 3d" like how they made the conductors so much smaller and denser. sadly we probably want get that story for a another 10 year's or more
That's called HIGHLY classified IP at this point. Yeah, you'll probably never hear how this is done for a few more years.
But I guarantee you that some entity in some country is trying to hack into TSMC systems to get a hold of this IP.
@@johndoh5182 Thanks for the answer.
I think it is similar in concept to cold welding, which was discovered back in the 40's.
Just replaced my 5900X with this 5800X3D. I love it.
Still waiting on a 5950X3D
I want to push my current system to its actual limit and to allow the god awful DDR5 modules to mature and reduce CL by 40%
Then wait for zen4! It's coming this fall
@@TheMakiran that is AM5 that means new system which also mean NO!!
A 5950X3D is a drop in replacement and what i both want and need to exist otherwise its the 5950x and that is a piece of crap in comparison to what a 5950X3D would be
@@commanderoof4578 15%-20% difference would make it obsolete?
@@TheMakiran yes actually it does because of my use cases
We are talking about the 5950x and a 5950X3D and so it should instantly be presumed i am not just some one that watches videos and plays games and thats all otherwise a 5600x fits perfectly for that
I need the cores of the 5950X, i need the Cache of X3D and i need the per core performance which also ties into the Cache size as it accelerates what i do and better uses the clock cycles
For my use cases it’s more like a 40% increase over a 5950x
@@commanderoof4578 oh sure then
Future Metaverse AI Civilization:How were we created?
Ancient Metaverse: Talks about humans/aliens that created 3D V Cache
Thank you for this presentation. It was very interesting. In regards to shaving the die portion, does that not reduce effectiveness of the remaining die? How is it able to match the performance of an unshaved die?
And if there is no difference between the two then couldn’t we increase the output of usable dies by vertically splitting them? You can even hybrid bond them back if it isn’t a two to one ratio.
Chips are not 3D. The usable transistors are just on one surface of the entire die. The rest of the die is completely without function, just a block of silicon.
People have been thinning dies forever by sanding them. Extreme overclockers do this to reduce the distance the heat has to travel through silicon and get to the cooler, hoping for better temperatures. They call it die lapping.
You can theoretically shave it down to just a few atoms thick, but you know from larger scale experiences in your own life how hard it is to make something thinner without breaking it.
@@BSEUNHIR Well not exactly on one side, the interconnects are, but the actual transistors are inside, and you can thin it too much and damage the transistor layers. Die thinning is a really dangerous thing, must be perfectly flat, not too shallow and not too deep.
Intel did their own die shaving back on 10th Gen K SKUs. For them however, it was as a heat management measure. The thinner die allowed for the heat to escape faster.
@@blkspade23 But this wasn't die splitting because you have 2 horizontal layers of transistors to produce 2 separate die on that same layer of silicon.
I'm also wondering about the die shavibg
The explanation is very extensive yet super simple at the same time, so it's much easier for a person like me that knows nothing about this technology to actually understand it, just one question tho, how are you be able to write backwards ?
The video is mirrored 😊
It might be a clue that everyone who does these "write on glass"-videos appears to be left handed :P
If Robert was my teacher I would probably be a scholar at this point
Thank you robert for explaining it in such an easy format. We need more such videos for everyone to have some basic knowledge about the products they are planning to buy. I hope amd will be able to provide us with some unlocked 3d v cache cpus soon after this, possibly with zen 4 or zen 5. That would be the icing on the cake.
I wonder if heat can be an issue to break to the bond between layers.
That is surely something they can test with heat cycles and would not worry about that, probably the same silicon quality is used to minimize the heat induced stretching. But what has to be considered is that another die on top will consume power. And this is why the X3D has 200 Mhz lower clocks compared to the standard 5800X, in order to maintain the same TDP and heat output, and also the heat of the CPU die itself need to pass through the cache die to get cooled, so they might have problems with higher heat on the CPU die itself - overclocking could damage it easier.
Main reason these chips will not be able to be over clocked. Great question though! AMD announced this not to long ago.
Probably why it is clocked so low out of the box
I hope they use this in Zen 4 , cant wait to buy a new rig , its gonna be awesome! 💪
My i7 920 is at the end of its life even if OCed to 4,1ghz.
Would have been awesome to provide more details than this surface level explanation. How exactly do you make the die connections? How do you handle the heat output?
this videos are Superb!!!
nobody else do this
LOVE U GUYS!!
Hbm memory amd
Hbm from 10 year's
I loved the explanation thank you , it can be used on everything like i already guessed since it already as been an adaptation.
My next machine will arise from your old ashes it will show things clearly i swear
Thank you, Lisa!
You have a great TEAM and amazing products.
Today I learned: computer with long blue line is slow :D
Can it be delidded without der8auer ripping off the cache block?
Can't wait until he tries!
@ £449 it better be fast!
I'm dumb but I can still understand this very well,he's a good teacher.
Playing league and only thing I can say let's ff right now AMD started another evolution of technology gg
There is only one problem:
You showed us a 5900x3D prototype - we need it!
I work in Aerostructure manufacturing and I'm familiar with what you're talking about called: "Wringing" where 2 very flat parts placed together interchange electrons through molecular attraction 🧲 but there's no magnetism involved! We do this daily 😌
i just realize that gauge block use this too
@@NKG416 yup! I love gage blocks i use them every day.
No one has noticed that he actually writing from mirror perspective..
Good skills..
1 year late, but they can flip the video after recording it.
I couldn't think that.. But.. How the hell 1 year just passed???
@@jaypatel0088 lmao time flies bro
@@leeham6230 flies? Faster than flash??.
dude can write in mirrored letters
I speculate this legendary CPU is going to show it's true potential in the next 2-5 years when GPUs would become roughly 2 to 4+ times faster than what they are now.
For now almost all GPUs will run at almost 100% utilization at all common screen resolutions when you pair them with this CPU and this is the reason users might not see the big difference today when you compare this system with other CPUs like Core i9-12th gen something. The reason for this is high core and clocked non-v-cache Zen 3 CPUs have already pushed current generation GPUs to its limit. Because in theory (and I don't see a reason why that won't be in practice), 3D-Vcache based CPU should be capable to draw bazillion times more draw calls than what is currently required to push the current gen GPUs. I predict the difference between say Core i9-12900k no matter the overclock (6 GHz? doesn't matter) and stock 5800X3D is going to become progressively larger as the time goes by (with 5800X3D keeps approaching more and more frames per second).
Date: IST 29-March-2022 - 07:02 PM
unfortunately by that time, better IPC from zen5 beyond as well as wide adoption of ddr5 will have exceeded the performance of this chip. Bottomline is, it needs to perform NOW, much like the competition is doing.
But hey, if that is indeed what will happen, then good for those who are planning to buy it now and plan to keep it for multiple years without upgrading. It is indeed the best and last hurrah of the am4 platform in terms of gaming after all.
You are not considering that latency is not the only limitation to memory access. There is also the bandwidth. So I guess faster DDR5 with lower latencies will alleviate the cache advantage, even though today it does not do much still, similar to how DDR4 2100 was barely matching the latest DDR3.
@@obeliskt1024 Future CPUs of that time will indeed be better, but I was talking about todays CPUs vs 5800X3D in future.
@@marsovac I bet $100 that the DDR5 of next 4 years won't reach L3 level latency of todays CPU. It's almost physically impossible in current paradigm . Unless we would have option for installing DRAM chip size of a quarter of a nail or something like that into the CPU die itself, it won't happen.
You will need DDR5 10000 MT/s in quad channel to reach the L3 bandwidth of 5800X3D and even then memory latency will be at least 5 times slower with DRAM.
Not only that, read and write transfer between L3 and other CPU cache is simultaneous. It means many read and write operations can happen simultaneously. Afaik DRAM either does read or does write operation at a time.
@@deleater It never will, but it can make up for it with frequency/bandwidth in respect to the DDR4. The same latency thing happened with DDR3 vs 4: CAS 9 vs today CAS14, and still DDR4 is now noticeably faster than DDR3 ever was. My point is that upgrading the memory on a 12900K to some fast DDR5 might offer it scaling that the VCache will give today. Although the VCache does not cost as a memory upgrade, so it perfectly makes sense if you want to upgrade today an old ryzen system with the X3D, especially since DDR5 is not an option for current gen AMD.
4:50 Does anyone know what exactly this process is called? Would love to just read about this at night instead of sleeping. Is this the same process called cold welding where two metals that aren't oxidized would weld together if they touch in vacuum?
Maybe a sort of interposer juste like HBM... Hard to say..
I would say they might be using a non oxygen environment
Because when metal isn’t oxidised it will weld on contact
It's called "van der Waals force".
You can Wikipedia that, I just checked. There's a pretty good explanation.
@@danieloberhofer9035 It seems to add up. Good find.
@@danieloberhofer9035 Awesome thanks this will make up for a great 4am research material.
I still find it very sad that you did not release the 5950X3D.
You can use it to both, playing games at 8 cores and 16c to do the work you need...
Been thinking about 3D VCache and I have a question!
Wouldn't it be a good idea to implement the cache chip in reverse? By this i mean having a "trench" on the substrate where you place the cache chip and then put the CPU chiplet on top of it instead of the cache on top of the CPU, you could possibly even then have 2 cache chips, one above one below, though my idea here is to avoid the heatspot issues by having the cache below the CPU chiplet to enable the CPU to be directly next to the heatsink instead of adding distance and thermal "soaking" areas with the current approach.
I am guessing it would be too difficult to get interconnects going through/via the cache to the die on top and there would a latency penalty from having the die further from the substrate. An interesting idea though.
@@Je-kg8up the distances remain pretty much the same, in fact could improve with die thinking which would be a good idea to do as the cache does not get as hot as the cpu, so it can really be thinned without much thermal considerations, a this point the structural integrity would likely be the limiting factor.
For a split second I thought it was the other guy, with multiple job skill sets...
Bro is making this video from shadow realm 💀💀
1:57 man's writing backwards!!!
Video is flipped horizontally.
Witch, Witch!! :D
I am impressed with your ability to write backwards on the screen.
He wrote normally. The video editing mirror the image again.
@@calvint3419 /swoosh
It might be harder to manage the heat from a system like this, however if theres a massive nearly generational leap in performance then as long as its similar in heat output to the rest of the Ryzen family I dont see why there would ever be a need to overclock the chip.
Seems like you were correct in your assumption because they don't allow overclocking on this CPU.
Excellent explanation and amazing innovation, great job AMD.
if your calling the vcache L3 and not L4 is this type of L3 not slower than on die L3? I assume it is, but because your stacking it on top it gives you alot more L3 compared to before which it's benefit is you stop fetching from RAM
Anandtech has a video about Milan x woth 3d stock cache, barely any difference in latency, so just added l3
@@malathomas6141 yeah that's what I was thinking, The stacked cache used as L3 is just a little slower than standard on die L3 but because you can have twice as much or more cache in comparison to standard on die L3 cache the system can work faster because it's not fetching as much from RAM.
This video is amazing and seeing you genuinely excited about it is the best part. X3D truly is amazing.
Cool tech, but massively disappointed that you didn't give us higher core count versions. 😞
Thanks for making educational content would love to see more e
All of this makes me just even more excited for Zen 4.
I'm interested in their new line of GPUs if they're going to use the 3D architechture. We could see some huge gains.
They're Chiplets, but they decided not to stack the memory on these first cards. It's very possible that their 7950xtx or whatever they will call it has that. But apparently they didn't feel it needed that boost for the price to add it.
June 2024. I got a whole new internal PC parts including case. I bought an AMD Ryzen 9 7950X3D 16 core CPU. Just remember to install the AMD Adrenaline Software. It will install the two AMD 3D V-Cache Optimizer Services to run in the RAM to make V-Cache always active when it needs to work.
5700X3D Gang
Damm Robert, you really went beyond. Great video. 9/10, just needed to put shrek on it to be perfection.
I see Johnny Sins has a new job now :D
Guys please don't become intel like monopolist that makes unsustainable pricing on your products we love amd for what this is and we love technology that stays behind it
I am pretty much sure AMD will use 3D V-Cache in the next gen and probably even upcoming PS5 Pro consoles. 3D SRAM cache will be a key player in the future and will play significant role not just in the gaming CPUs especially when SRAM is for now not going to be shrink even further unless new type of transistors r adopted and widely used.
I am telling you, I have had AMD for years now for gaming and for me it is way better than Intel. I have a desktop with a Ryzen 5, RTX 2070 Super, does pretty good. Laptop with a Ryzen 7, RTX 3060 that does better. Just researched today and found out my desktop can handle a RTX 4090, so next month I will see what life is like with that and a 8k OLED. Christmas I will teat myself to a new something with what he is talking about. Excellent video, love science.
As the Chair of the IEEE Semiconductor Roadmap ( IRDS ) Packaging Integration section and a 30+ yr veteran of developing Advanced Packaging technologies and their transition to High Volume Mfr. ( not just for Micro Processors and Smart Phones - both digital and RF but also for HBM / HMC & SuperComputers, my inventions now amount to over $30 billion / yr of Semiconductor production worldwide ), I must TAKE EXCEPTION to AMDs PUFFERY. Shame on Lisa Su who used to be a jr. PhD ( hired from MIT ) at Motorola where in the '90s ( when neighbor AMD was virtually DEAD ) we were doing most of this work, for letting people under her getting carried away w/ their FLUMMERY.
Neither AMD nor its offshore Foundry are the inventors or first users of either micro Pillar ( invented in 1994 by yours truly at Moto, by 1996 in Moto FlipPhones out of a fully Robotic line in AZ which too I had to design & develop ) or Hybrid Bonding - Copper ( HBC, invented by Paul Enquist of Ziptronix, NC around 2011, in use by 2017 at SONY in Cameras for SmartPhones ). SONY too was the first to split up one large Camera Chip that had included both the Imaging and the Processor sections ( requiring finer node mfr. into 2 parts and connecting them by HBC ) thus cutting cost. In terms of process capability SONY still leads AMDs offshore Foundry ( whose capability is described in the Video above ) when it comes to the "pitch" ( spacing ) of their HBC connections by over 2X. The same concept is now applied to V cache by taking the hard to shrink SRAM out of the Processor.
And BTW the Dutch Physicist ( whose 100 yr old principle was used by Paul E. to develop first DBC and then HBC ), that the AMD presenter refers to as mere Johannes ( perhaps because that was all he had been supplied with by their PR dept. ! ), is better known to any Science or Engr. undergrad as Van der Waals. The force that sticks the hybrid part of the die to die bond ( btwn the dielectric INSULATING covers on the two dies ) is called van der Waals force. But the actual CONDUCTING bond btwn the two dies on the mating Copper pads sticking out through the insulator layers takes place by a Metallurgical process called Grain Growth and Twinning. For that to happen in a reliable way, first the dies and wafers to be bonded by HBC have to be prepared by quite finicky pre processing called CMP..
The actual lP for the DBC / HBC process is now owned by a 30 yr old US HQed Packaging tech / licensing Co. in Santa Clara, CA called XPeri.
After all this hoopla the improvement in electrical performance ( bandwidth, throughput, power eff. ) w/ V cache is around 12%. In contrast a British start up has come up w/ AI chips ( incl. Accelerators ) also using HBC and fabricated at the same offshore foundry, BUT w/ a more intelligent electrical design shows an improvement in AI Benchmarks for Training & Inference of 40% !
Very interesting, would love to see more videos in this style!
Lux the Droid robot loads fast enough loaded in 300MB's of CACHE ^p Say 700FPS
The size issue is not one clearly defined by progress, but defining
reality though pre tested hardware? Source of future security &
reliability RS
So Security 'LUX' The DROID : Really does float in 32MB floating L3 RAM Tables
I'm imagining the AM12 with Pyramid Stacking technology.
A Pyramid shaped CPU that requires a cone shaped cold plate to allow huge 3d stacked chips.
Cache in the centre and cores around the top so the centre isn't as thermally dense.
Can't wait for the AMD Illuminati Ridge generation.
Wait but it just explains the importance of l3 cache but doesn't explain the importance of having a 3d v cache.
So a traditional l3 cache with 96mb vs a 3d v cache with 96mb
Lux the Droid robot loads fast enough loaded in 300MB's of CACHE ^p Say 700FPS
Closely have to explore 3D V-Cache, knowing AMD is always innovating, one chip in hand of that kind would be evident whatever the benchmarks are stating
I own rtx 3090 and play games at 1400p but the GPU is never pegged at 99%. It is fluctuating from 60% to 90%, this makes my games run like crap. I need a cpu with at least 2x the ipc than the i9 9900k I have.
AMD should re-add the 3DNow! as CPU support with 3D V-Cache Technology! 🙂
Absolute master class technology and explanation for the average viewer to know what's really going on !
Hats off to you sir !
Very well explained. Thanks, it was so easy to follow along and understand. Would like to see more of this if possible.
I wonder if they have done shock/drop tests to make sure the bond doesn't break from the stack. It needs to be made Linus proof. Physicists can chime in if you know what you know.
it's become same metal chip when you do it like that so very, very linus proofed!
Hey Robert, we still wait for a CO fix on the 5000 CPUs, you know, that BSOD on low load/idle after standing 20 hours tuning it on high load and stuff… any news on that or we have forgotten about that feature? You know that feature that was at least 30% of the reason ppl bought the CPU.
Ugh... I could've used a bit more of a deep dive. You basically just said what was already said at Computex. You just said it a little slower than Lisa did :P
If you really want to be successful, don't disclose your success mantra. That's why nvidia is enjoying the market
(Surfaces that flat when together may even end up cold-welded, which is actually a problem for space ships)
The size issue is not one clearly defined by progress, but defining reality though pre tested hardware? Source of future security & reliability RS
if the cpu cores are going to be below and the memory on top
will the cpu cores be cooled from beneath the motherboard?
or could the memory be below with the cpu cores on top
so that the cpu core are cooled from above the chip?
maybe question is more relevant if it's many layers of memory and other stuff
on top of or below cpu cores
I'm curious how they'll tackle heat with different dies on dies. Perhaps some of those interconnects could be dummied out for solely heat transfer and soldered to an intermediary layer of copper that contacts the IHS?
Do I dare entertain the thought of AMD et al carving grooves into their dies and filling them with water???
I heard that they completely block OC. And the clock is also lower.
@@sonpham4119 For the 5800X3D this is true. AMD sent a notice to motherboard manufacturers to disable overclocking for the 5800X3D. I think in response to an inquiry by Gamers Nexus?, AMD said the reason for that was something about the Vcache needing strict adherence to 1.35V. And to stay within the same 105W TDP as the original 5800X, they reduced the 5800X3D's clocks to make up for the power draw of the extra cache.
They also said that this was solely limited to the 5800X3D, indicating that they already solved the issue but just didn't have time to engineer it into the 5800X3D...?
@@mahatmagandhiful Yup. Future V Cache products will likely have the V Cache on it's own (fixed) power line instead of having it draw from VCORE.
@@mahatmagandhiful If what the other person said is right (about cache and CPU cores both drawing from VCore), then AMD would not have been able to implement it into the 5800X3D at all, as it would require extra separate power lines that the existing socket AM4 motherboards do not have, requiring a revised socket and new motherboard. Remember, one of the points of buying this CPU is so you can get one last performance boost on your existing AM4 motherboard instead of having to replace it too. The AM5 socket and AM5 CPU packages have many, many more pins than the AM4 socket has, and a number of those pins are likely the separate power deliveries for the cache if what was said is true.
AMD can definitely beat NVIDIA by 3dvcache on GPU
Am I the only one tripping on the fact he's writing in double mirror mode? I can't figure out what the setup of the scene is lol
haha the RDNA3 MCM hint, anyway love the way you explain things.
This sounded like a premonition on whats cooking..
What about the latency? I can't find any exact information on the difference between 3dv-c and traditional on-die.
Good presentation. I have one question, how additional cache of 64 Mb compete with 16, 32 or 64 !Gb! of RAM, that's something weird...
That's because of all the thousands of lines of code and data that a program or game may store on the CPU cache and RAM, not all of it is accessed at an equal rate -- never. Some chunks of memory are accessed literally millions of times per second, while other chunks of memory may only be accessed on a lesser frequent scale, i.e. thousands of times per second.
The bits of memory that are used the most frequently are stored on the L1 cache of the CPU, which is the fastest and lowest latency cache. Bits that are accessed frequently but not nearly as much as the most accessed, are stored in the L2 cache. The rest of the frequently read code is then stored in the L3 memory, and everything else gets stored in the memory of course. L2 cache is slower and higher latency than L1, L3 is also even slower than L2 and higher latency, and of course, the RAM is the highest latency and worst speed of all. RAM is always slower than cache.
By having a larger L3 cache size like with the Zen 3 3D V-Cache CPUs shown in the video, more and more of those frequently accessed bits of data, that would have been stored in RAM since the cache was full, are stored in the larger L3 cache instead, providing a performance boost to the application, depending on how memory-intensive the application is (in terms of data speed, not data capacity).
It doesn't matter how much memory the program uses, a program will always have very often used bits of code, as well as code that isn't nearly as used often, with the difference between the two being orders of magnitude.
More RAM will only speed things up if the program was using enough RAM that there was very little/no free memory left and page ins and outs to the pagefile on the HDD/SSD had to occur because of it. An SSD may be very fast compared to a HDD, but an SSD is still hundreds to thousands of times slower than memory, both latency and bandwidth wise.
Hierarchy of cache/memory speeds and latencies:
L1 > L2 > L3 > System RAM > Pagefile.
@@bestage9429 Thanks you for such detailed mini-review of interaction between CPU cache, RAM and SSD/HDD. I'm not a programmer/technician and one thing I cannot understood - how CPU decide what code it will place in L3 cache and what will be in RAM? (hypothesis is that CPU has it's own algorithm? or it's not how all works...).
P.S. Sorry for my English, I'm from Ukraine🇺🇦 and don't know English well 😔
@@Charodiy_UA This one is a bit of a complicated question to answer for me, but basically there are algorithms and logic in the CPU to determine what bits of memory will be placed in L1 cache, what will go in L2, etc. One such algorithm is called prefetch, where memory access patterns are used to predict what blocks of memory will be needed next, and store them in the cache.
@@bestage9429 It's really interesting 👍, now I want to read more about this complicated process and will learn more to know how all this communication between CPU, RAM, SSD, Videocard work and of course what role take Motherboard in it!
Not that worried about being a gaming champion, if you talk to me about general overall champion in all compute areas then I do care!
Oops, he's wearing his watch on his right hand. (Now we know how the magical writing technology works :P)
Does thinning the Zen 3 die cause any durability issues?
You could place a small plate of synthetic diamonds, since they have a higher thermal conductivity and those that are made by machine are cheap.
the best ihs would be that
when does a laptop arrive?
a 7945HX3D
Игры не используют процессор совсем, там 2 процента на нём, скорее это для майнинга крипты.
from 3DNOW to 3D V-cache, what an evolution AMD has been through
Both were incredible but one is actually successful.
Ahhhhh he said glue!
the most impressive part is his ability to write backwards on the glass so well
I'm impressed as well but then I realize.......
I think the video is flipped
I went from Intel to AMD a few months ago and haven't looked back since.
world faster 1080p gaiming cpu respect lisa su!!!
Just installed my 5800X3D right now.