VLSI Physical Design: Powerplan

Website: www.vlsi-backe...
Power plan
Power planning is done to provide uniform supply voltages to all cells in the design. The primary objective of power planning is to ensure that all on chip components (blocks, memory, I/O cells etc...) have adequate power and ground connections.
-Power Management Techniques
1. Core Power Management
2. I/O Power Management
-Inputs of Power plan
-UPF Contents
-Special cells: power switch, Isolation Cells, Retention Registers, Level Shifter cells.
-Power Reduction Techniques: Power gating, Clock Gating, Voltage and Frequency Scaling, Substrate Biasing, Multiple Threshold Voltages, Multiple Supply Voltages and memory partitioning.
Types of Power Dissipation: static Power Dissipation and Dynamic Power Dissipation.
-IR Drop, Electromigration.
-Power plan checklists.

[@jagatpatiraiguru9806]

Very Nice Explanation With good Colorful Diagram Sir ... Thankful to you sir . The lectures and contents are really very helpful and I learned a lot from this. Thank you so much sir

[@gayathrilasyamarkapuram2160]

concept is clear with relevant content ...waiting for more videos

[@redheatredheat9906]

One of the most detailed & clarity-driven videos I have seen. Although you can never cover everything in something as vast as PD, but still this is one the best videos series I have seen. Thank you so much

[@FerozAhmed_PhysicalDesign]

Thanks

[@mrbeast6696]

Good explanation

[@avvarutheja]

If you are using upf and the design had 10 different power nets, then how does power rings will be created? Across each power domain you will create domain specific power ring? Also, when you have header/footer how does the power distributed to power rails?

[@FerozAhmed_PhysicalDesign]

Common power ring will be there.

[@saijagadeesh1708]

Sir , can u please tell why we will place level shifter at receiver end only

[@FerozAhmed_PhysicalDesign]

It will Affect the timing if we place near transmitter.

[@user-tj9nm7ee2x]

Why is your website not working? It used to open but now it shows error.

[@jagatpatiraiguru9806]

Sir Can you kindly suggest a good Book for reference - Physical Design VLSI subject ??

[@FerozAhmed_PhysicalDesign]

You can find on libgen and pdfdrive.com

[@rajgandhi4042]

What is the meaning of, Top to bottom approach is used for the power analysis of flatten design, while bottom up approach is suitable for macros? Can you elaborate it please.

[@FerozAhmed_PhysicalDesign]

Sorry for the delay, its a huge topic within but I'll tell you in short, it is like we have to take chiptop and partition it and do each block PnR. And bottom up it starts from block, do PnR of each block and then merge and make the Floorplan.

[@dhirajthalladi4934]

Sir, how to calculate the width of stripes and rings and how many power gaters required

[@FerozAhmed_PhysicalDesign]

this can't be answered directly as it has multiple factors to be considered when we calculate all the parameters.
download the document which i've shared. hope this helps a bit.
community.cadence.com/cfs-file/__key/telligent-evolution-components-attachments/00-29-00-00-00-02-15-51/Powercalculation.pdf

[@dhirajthalladi4934]

Thank you

[@naveenas7437]

which company are u working for

[@vlsi_ic1237]

i love you

[@yeshwanthkatrapati533]

Can you do powerplan using tool

[@FerozAhmed_PhysicalDesign]

Sorry mate, I don't have tool access for doing so.

[@yeshwanthkatrapati533]

@@FerozAhmed_PhysicalDesign I've tool access
Can you help me in doing so

[@FerozAhmed_PhysicalDesign]

@@yeshwanthkatrapati533 no time man, working for Qcomm. Hope you know the work culture.

[@yeshwanthkatrapati533]

@@FerozAhmed_PhysicalDesign Thank You
Lemme know if you're a little bit free
Just I need how to do power grid after boundary cell placement