Hi , At signal routing stage , during Global routing whether the entire design (CTS completed design) is divided into G-cells or only the availlable routing area?
Can you please be a little more specific? I didn't probably get you properly. Do you mean what happens to the total resistance if we use multiple metal layers for a net? Or do you want me to brief about the magnitude of change in resistivity as we go for higher layers?
@@jairamgouda actually my question if M1 upon M2 like that if we connect what will be the resistivity will varry and which metal have more resistivity and why ??
@@sardharvankunavath1988 Yes, I got you. Basically as I have explained in the video, the resistance of the metal M0 is the highest in metal layers and the capacitance is the lowest. Similarly the highest metal used in the chip maybe m5 or M10 or M 18, whatever it is, wil have the highest capacitance and lowest resistance. Why? Because the width of the metals usually increases as we go from M0, M1 to top metal in the design.
Very good concept about routing layers
Thank you for the video!! Great visual representation and explanation!!
Very good concepts 🔥🔥
Great Video Sir !!!
Thank you
Make a video how we can calculate pitch offer and spacing between metal layers
Nice
Hi ,
At signal routing stage , during Global routing whether the entire design (CTS completed design) is divided into G-cells or only the availlable routing area?
Entire design
How you are saying that Lower metal layer offer high capacitance and Higher metal layer offer less resistance? Please give explaination on that
Sir i have some questions related to pd..how to reach you to get answers..ur explanation are 🔥🔥🔥
You can mail me
if we connect metal1 ,metal2 and metal3 can u compare their resistivity ??/
Can you please be a little more specific? I didn't probably get you properly. Do you mean what happens to the total resistance if we use multiple metal layers for a net? Or do you want me to brief about the magnitude of change in resistivity as we go for higher layers?
@@jairamgouda actually my question if M1 upon M2 like that if we connect what will be the resistivity will varry and which metal have more resistivity and why ??
@@sardharvankunavath1988 Yes, I got you. Basically as I have explained in the video, the resistance of the metal M0 is the highest in metal layers and the capacitance is the lowest. Similarly the highest metal used in the chip maybe m5 or M10 or M 18, whatever it is, wil have the highest capacitance and lowest resistance. Why? Because the width of the metals usually increases as we go from M0, M1 to top metal in the design.
@@jairamgouda okay tqs for ur valuable response