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thankyou

thanks it was very helpful

Really not understand the main difference

Hi in your simulation you can see immediately the input and the output, but my simulation gives me the graph after a long time, do know where the problem might be?

very informative

You have mentioned the hold equation the opposite way. T(clk-q) + T(comb) > T(hold)

Very good explanation

HELP ME

First of all BCD is equivalent to Decimal number correct your title

bad teaching.totally useless

Thank you.

You are amazing👍

how many gates in gaafet transistor with backside power delivery

Thanks for the video. Do you have one discussing the timing requirements for the ICGC cell? Even with the negedge latch, the enable cannot be toggled very close to the posedge of the clk.

Thanks

How can we know that the contact resistance are in parallel

Hii...I have been looking your content and explanation. these are very understandable. Can you please do on the topic of slack and calculations related to it.and also remaining Indepth concepts of pd.

Hi- How high Vth cell are low power cell ?

Thanks for the video. How are you getting negative swings in the output using a single (+ive) power supply?

Can anyone tell me how palladium emulator emulate a design ?

1:40 1990,1992, 1994. What is on first, who's on second.

Really good video! Would it be possible for you to make an over view video on what are the different types of software (EDA or physics based) used during the design process and where they are used?

Thanks 🙏🙏🙏 for great explanation

Superb explanation bro...

sir i am not able to get uniform decoder, uniform encoder, and analog design filter components in the library browser

Very good explanation

Sir your explanation is so good.👍👍 I found this video after watching 9-10 another senseless videos

Thanks Jairam :) This is a very helpful video :)

It would be much more useful if you could include CMRR PSRR calculations etc.

One of the best videos on Asic design flow

Good presentations. Thanks for posting these videos.

Thank you so much. It is really helpful ^^

can't understand

You didn't explain the second part well enough....first part was fine

What if the antenna violation is on the topmost layer??? How do you solve antenna violations for vias?

Could you provide a Google Drive file with the model MOD? The process has changed, and it now involves multiple files instead of just the model. The video is outdated, and I need the updated files.

Thanks, Jairam for the video. Appreciate your effort.

More visual representation, interlinking between different topics will be good along with Industries current view. Power, Logic, Memory's and RF DTCO are complexly deferent, we clearly should present without using catchy words.

Can you post the tutorial

1:30 so u r saying if voltage at gate is 1, the output from drain will be 0.

can you please explain why you have written mov ax,data mov ds,ax and lea si,x

But sir, how to determine threshold voltage ?

Very good video . Learned a lot through this series so far.

bro the pulses uses is the same all 4 trans.. how its control the switching to differentiate the flow during the positive sequence and negative sequence.??

Please, can you make vedio on adaptive delta modulation

What is forward annotation? Dofferene between forawd and bacward?

Nice

Hi sir,can you explain physical verification

how about terminals ? meaning, do we need pins to place terminals?