Pretty cool demonstration of a 4-Bit parallel shift register. Nice touch with the Load signal enable switch. Other videos don't cover that kind of stuff until much later.
A D flip flop is an SR latch (just with S and R tied together and one of the lines inverted, and with extra clock input) .. SR latch does not connect to clock so this wouldnt make sense for SR latch
u said if clock is 1 then when D is 0 then output will be 0 but when u said when theres no clock the output will remain at its previous output can u explain this part when theres is no clock?
When there is no clock ( clock = 0 ) then the register does not look at D at all. It only looks at D when clock switches from 0 to 1... also called the rising edge of the clock. If clock = 1 and D = 0, then output Q = 0, however if D changes from 0 to 1 before clock goes back to 0, Q does not change because it only changes when clock switches from 0 to 1.. not when it is 1 and not when it changes from 1 to 0
Pretty cool demonstration of a 4-Bit parallel shift register. Nice touch with the Load signal enable switch. Other videos don't cover that kind of stuff until much later.
thank you, you're saving my semester😌
Thank you! Good explanation, answered my questions!
nice and slow pal... just the way i like my explanations
I usually encourage my students to use the settings to set the playback speed to 2X, but whatever works for you.
I wanna ask you that how can we design this circuit without gating the main clock? Thanks.
I've never heard about disabling a clock from sending signals.
how can i do it using combinational circuits?
God bless you!
Does this also work for SR latches??
A D flip flop is an SR latch (just with S and R tied together and one of the lines inverted, and with extra clock input) .. SR latch does not connect to clock so this wouldnt make sense for SR latch
im cooked
u said if clock is 1 then when D is 0 then output will be 0 but when u said when theres no clock the output will remain at its previous output can u explain this part when theres is no clock?
When there is no clock ( clock = 0 ) then the register does not look at D at all. It only looks at D when clock switches from 0 to 1... also called the rising edge of the clock. If clock = 1 and D = 0, then output Q = 0, however if D changes from 0 to 1 before clock goes back to 0, Q does not change because it only changes when clock switches from 0 to 1.. not when it is 1 and not when it changes from 1 to 0
can u tell me what im supposed to get from this video?
You can’t get anything from this video because you’re thick headed.
You should have shown an example how it is done .